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[people/ms/u-boot.git] / board / toradex / apalis_imx6 / apalis_imx6.c
1 /*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4 * Copyright (C) 2014-2016, Toradex AG
5 * copied from nitrogen6x
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/iomux.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/arch/mx6-ddr.h>
20 #include <asm/bootm.h>
21 #include <asm/gpio.h>
22 #include <asm/io.h>
23 #include <asm/imx-common/iomux-v3.h>
24 #include <asm/imx-common/mxc_i2c.h>
25 #include <asm/imx-common/sata.h>
26 #include <asm/imx-common/boot_mode.h>
27 #include <asm/imx-common/video.h>
28 #include <dm/platform_data/serial_mxc.h>
29 #include <dm/platdata.h>
30 #include <fsl_esdhc.h>
31 #include <i2c.h>
32 #include <imx_thermal.h>
33 #include <linux/errno.h>
34 #include <malloc.h>
35 #include <mmc.h>
36 #include <micrel.h>
37 #include <miiphy.h>
38 #include <netdev.h>
39
40 #include "../common/tdx-cfg-block.h"
41 #ifdef CONFIG_TDX_CMD_IMX_MFGR
42 #include "pf0100.h"
43 #endif
44
45 DECLARE_GLOBAL_DATA_PTR;
46
47 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50
51 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
52 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
53 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54
55 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
57
58 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
60
61 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
62 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
63
64 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
66 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
67
68 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
69 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
70 PAD_CTL_SRE_SLOW)
71
72 #define NO_PULLUP ( \
73 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
74 PAD_CTL_SRE_SLOW)
75
76 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
77 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
78 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
79
80 #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
81
82 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
83
84 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
85
86 int dram_init(void)
87 {
88 /* use the DDR controllers configured size */
89 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
90 (ulong)imx_ddr_size());
91
92 return 0;
93 }
94
95 /* Apalis UART1 */
96 iomux_v3_cfg_t const uart1_pads_dce[] = {
97 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
98 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
99 };
100 iomux_v3_cfg_t const uart1_pads_dte[] = {
101 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
102 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
103 };
104
105 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
106 /* Apalis I2C1 */
107 struct i2c_pads_info i2c_pad_info1 = {
108 .scl = {
109 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
110 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
111 .gp = IMX_GPIO_NR(5, 27)
112 },
113 .sda = {
114 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
115 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
116 .gp = IMX_GPIO_NR(5, 26)
117 }
118 };
119
120 /* Apalis local, PMIC, SGTL5000, STMPE811 */
121 struct i2c_pads_info i2c_pad_info_loc = {
122 .scl = {
123 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
124 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
125 .gp = IMX_GPIO_NR(4, 12)
126 },
127 .sda = {
128 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
129 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
130 .gp = IMX_GPIO_NR(4, 13)
131 }
132 };
133
134 /* Apalis I2C3 / CAM */
135 struct i2c_pads_info i2c_pad_info3 = {
136 .scl = {
137 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
138 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
139 .gp = IMX_GPIO_NR(3, 17)
140 },
141 .sda = {
142 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
143 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
144 .gp = IMX_GPIO_NR(3, 18)
145 }
146 };
147
148 /* Apalis I2C2 / DDC */
149 struct i2c_pads_info i2c_pad_info_ddc = {
150 .scl = {
151 .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
152 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
153 .gp = IMX_GPIO_NR(2, 30)
154 },
155 .sda = {
156 .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
157 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
158 .gp = IMX_GPIO_NR(3, 16)
159 }
160 };
161
162 /* Apalis MMC1 */
163 iomux_v3_cfg_t const usdhc1_pads[] = {
164 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
166 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
167 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
168 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
169 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
175 # define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
176 };
177
178 /* Apalis SD1 */
179 iomux_v3_cfg_t const usdhc2_pads[] = {
180 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
183 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
186 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
187 # define GPIO_SD_CD IMX_GPIO_NR(6, 14)
188 };
189
190 /* eMMC */
191 iomux_v3_cfg_t const usdhc3_pads[] = {
192 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
193 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
194 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
195 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
196 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
197 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
198 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
199 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
200 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
201 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
202 MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
203 };
204
205 int mx6_rgmii_rework(struct phy_device *phydev)
206 {
207 /* control data pad skew - devaddr = 0x02, register = 0x04 */
208 ksz9031_phy_extended_write(phydev, 0x02,
209 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
210 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
211 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
212 ksz9031_phy_extended_write(phydev, 0x02,
213 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
214 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
215 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
216 ksz9031_phy_extended_write(phydev, 0x02,
217 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
218 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
219 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
220 ksz9031_phy_extended_write(phydev, 0x02,
221 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
222 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
223 return 0;
224 }
225
226 iomux_v3_cfg_t const enet_pads[] = {
227 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
230 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
235 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
237 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
239 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
240 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
241 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
242 /* KSZ9031 PHY Reset */
243 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
244 # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
245 };
246
247 static void setup_iomux_enet(void)
248 {
249 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
250 }
251
252 static int reset_enet_phy(struct mii_dev *bus)
253 {
254 /* Reset KSZ9031 PHY */
255 gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
256 mdelay(10);
257 gpio_set_value(GPIO_ENET_PHY_RESET, 1);
258
259 return 0;
260 }
261
262 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
263 iomux_v3_cfg_t const gpio_pads[] = {
264 /* Apalis GPIO1 - GPIO8 */
265 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
266 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
267 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
268 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
269 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
270 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP),
271 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN),
272 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
273 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
274 };
275
276 static void setup_iomux_gpio(void)
277 {
278 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
279 }
280
281 iomux_v3_cfg_t const usb_pads[] = {
282 /* USBH_EN */
283 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
284 # define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
285 /* USB_VBUS_DET */
286 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
287 # define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
288 /* USBO1_ID */
289 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
290 /* USBO1_EN */
291 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
292 # define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
293 };
294
295 /*
296 * UARTs are used in DTE mode, switch the mode on all UARTs before
297 * any pinmuxing connects a (DCE) output to a transceiver output.
298 */
299 #define UFCR 0x90 /* FIFO Control Register */
300 #define UFCR_DCEDTE (1<<6) /* DCE=0 */
301
302 static void setup_dtemode_uart(void)
303 {
304 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
305 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
306 setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
307 setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
308 }
309 static void setup_dcemode_uart(void)
310 {
311 clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
312 clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
313 clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
314 clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
315 }
316
317 static void setup_iomux_dte_uart(void)
318 {
319 setup_dtemode_uart();
320 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
321 ARRAY_SIZE(uart1_pads_dte));
322 }
323
324 static void setup_iomux_dce_uart(void)
325 {
326 setup_dcemode_uart();
327 imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
328 ARRAY_SIZE(uart1_pads_dce));
329 }
330
331 #ifdef CONFIG_USB_EHCI_MX6
332 int board_ehci_hcd_init(int port)
333 {
334 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
335 return 0;
336 }
337
338 int board_ehci_power(int port, int on)
339 {
340 switch (port) {
341 case 0:
342 /* control OTG power */
343 gpio_direction_output(GPIO_USBO_EN, on);
344 mdelay(100);
345 break;
346 case 1:
347 /* Control MXM USBH */
348 gpio_direction_output(GPIO_USBH_EN, on);
349 mdelay(2);
350 /* Control onboard USB Hub VBUS */
351 gpio_direction_output(GPIO_USB_VBUS_DET, on);
352 mdelay(100);
353 break;
354 default:
355 break;
356 }
357 return 0;
358 }
359 #endif
360
361 #ifdef CONFIG_FSL_ESDHC
362 /* use the following sequence: eMMC, MMC, SD */
363 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
364 {USDHC3_BASE_ADDR},
365 {USDHC1_BASE_ADDR},
366 {USDHC2_BASE_ADDR},
367 };
368
369 int board_mmc_getcd(struct mmc *mmc)
370 {
371 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
372 int ret = true; /* default: assume inserted */
373
374 switch (cfg->esdhc_base) {
375 case USDHC1_BASE_ADDR:
376 gpio_direction_input(GPIO_MMC_CD);
377 ret = !gpio_get_value(GPIO_MMC_CD);
378 break;
379 case USDHC2_BASE_ADDR:
380 gpio_direction_input(GPIO_SD_CD);
381 ret = !gpio_get_value(GPIO_SD_CD);
382 break;
383 }
384
385 return ret;
386 }
387
388 int board_mmc_init(bd_t *bis)
389 {
390 #ifndef CONFIG_SPL_BUILD
391 s32 status = 0;
392 u32 index = 0;
393
394 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
395 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
396 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
397
398 usdhc_cfg[0].max_bus_width = 8;
399 usdhc_cfg[1].max_bus_width = 8;
400 usdhc_cfg[2].max_bus_width = 4;
401
402 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
403 switch (index) {
404 case 0:
405 imx_iomux_v3_setup_multiple_pads(
406 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
407 break;
408 case 1:
409 imx_iomux_v3_setup_multiple_pads(
410 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
411 break;
412 case 2:
413 imx_iomux_v3_setup_multiple_pads(
414 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
415 break;
416 default:
417 printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
418 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
419 return status;
420 }
421
422 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
423 }
424
425 return status;
426 #else
427 struct src *psrc = (struct src *)SRC_BASE_ADDR;
428 unsigned reg = readl(&psrc->sbmr1) >> 11;
429 /*
430 * Upon reading BOOT_CFG register the following map is done:
431 * Bit 11 and 12 of BOOT_CFG register can determine the current
432 * mmc port
433 * 0x1 SD1
434 * 0x2 SD2
435 * 0x3 SD4
436 */
437
438 switch (reg & 0x3) {
439 case 0x0:
440 imx_iomux_v3_setup_multiple_pads(
441 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
442 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
443 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
444 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
445 break;
446 case 0x1:
447 imx_iomux_v3_setup_multiple_pads(
448 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
449 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
450 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
451 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
452 break;
453 case 0x2:
454 imx_iomux_v3_setup_multiple_pads(
455 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
456 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
457 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
458 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
459 break;
460 default:
461 puts("MMC boot device not available");
462 }
463
464 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
465 #endif
466 }
467 #endif
468
469 int board_phy_config(struct phy_device *phydev)
470 {
471 mx6_rgmii_rework(phydev);
472 if (phydev->drv->config)
473 phydev->drv->config(phydev);
474
475 return 0;
476 }
477
478 int board_eth_init(bd_t *bis)
479 {
480 uint32_t base = IMX_FEC_BASE;
481 struct mii_dev *bus = NULL;
482 struct phy_device *phydev = NULL;
483 int ret;
484
485 setup_iomux_enet();
486
487 #ifdef CONFIG_FEC_MXC
488 bus = fec_get_miibus(base, -1);
489 if (!bus)
490 return 0;
491 bus->reset = reset_enet_phy;
492 /* scan PHY 4,5,6,7 */
493 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
494 if (!phydev) {
495 free(bus);
496 puts("no PHY found\n");
497 return 0;
498 }
499 printf("using PHY at %d\n", phydev->addr);
500 ret = fec_probe(bis, -1, base, bus, phydev);
501 if (ret) {
502 printf("FEC MXC: %s:failed\n", __func__);
503 free(phydev);
504 free(bus);
505 }
506 #endif
507 return 0;
508 }
509
510 static iomux_v3_cfg_t const pwr_intb_pads[] = {
511 /*
512 * the bootrom sets the iomux to vselect, potentially connecting
513 * two outputs. Set this back to GPIO
514 */
515 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
516 };
517
518 #if defined(CONFIG_VIDEO_IPUV3)
519
520 static iomux_v3_cfg_t const backlight_pads[] = {
521 /* Backlight on RGB connector: J15 */
522 MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
523 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
524 /* additional CPU pin on BKL_PWM, keep in tristate */
525 MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
526 /* Backlight PWM, used as GPIO in U-Boot */
527 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
528 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
529 /* buffer output enable 0: buffer enabled */
530 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
531 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
532 /* PSAVE# integrated VDAC */
533 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
534 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
535 };
536
537 static iomux_v3_cfg_t const rgb_pads[] = {
538 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
539 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
540 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
541 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
542 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
543 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
544 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
545 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
546 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
547 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
548 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
549 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
550 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
551 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
552 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
553 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
554 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
555 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
556 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
557 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
558 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
559 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
560 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
561 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
562 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
563 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
564 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
565 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
566 };
567
568 static void do_enable_hdmi(struct display_info_t const *dev)
569 {
570 imx_enable_hdmi_phy();
571 }
572
573 static int detect_i2c(struct display_info_t const *dev)
574 {
575 return (0 == i2c_set_bus_num(dev->bus)) &&
576 (0 == i2c_probe(dev->addr));
577 }
578
579 static void enable_lvds(struct display_info_t const *dev)
580 {
581 struct iomuxc *iomux = (struct iomuxc *)
582 IOMUXC_BASE_ADDR;
583 u32 reg = readl(&iomux->gpr[2]);
584 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
585 writel(reg, &iomux->gpr[2]);
586 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
587 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
588 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
589 }
590
591 static void enable_rgb(struct display_info_t const *dev)
592 {
593 imx_iomux_v3_setup_multiple_pads(
594 rgb_pads,
595 ARRAY_SIZE(rgb_pads));
596 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
597 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
598 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
599 }
600
601 static int detect_default(struct display_info_t const *dev)
602 {
603 (void) dev;
604 return 1;
605 }
606
607 struct display_info_t const displays[] = {{
608 .bus = -1,
609 .addr = 0,
610 .pixfmt = IPU_PIX_FMT_RGB24,
611 .detect = detect_hdmi,
612 .enable = do_enable_hdmi,
613 .mode = {
614 .name = "HDMI",
615 .refresh = 60,
616 .xres = 1024,
617 .yres = 768,
618 .pixclock = 15385,
619 .left_margin = 220,
620 .right_margin = 40,
621 .upper_margin = 21,
622 .lower_margin = 7,
623 .hsync_len = 60,
624 .vsync_len = 10,
625 .sync = FB_SYNC_EXT,
626 .vmode = FB_VMODE_NONINTERLACED
627 } }, {
628 .bus = -1,
629 .addr = 0,
630 .di = 1,
631 .pixfmt = IPU_PIX_FMT_RGB24,
632 .detect = detect_default,
633 .enable = enable_rgb,
634 .mode = {
635 .name = "vga-rgb",
636 .refresh = 60,
637 .xres = 640,
638 .yres = 480,
639 .pixclock = 33000,
640 .left_margin = 48,
641 .right_margin = 16,
642 .upper_margin = 31,
643 .lower_margin = 11,
644 .hsync_len = 96,
645 .vsync_len = 2,
646 .sync = 0,
647 .vmode = FB_VMODE_NONINTERLACED
648 } }, {
649 .bus = -1,
650 .addr = 0,
651 .di = 1,
652 .pixfmt = IPU_PIX_FMT_RGB24,
653 .enable = enable_rgb,
654 .mode = {
655 .name = "wvga-rgb",
656 .refresh = 60,
657 .xres = 800,
658 .yres = 480,
659 .pixclock = 25000,
660 .left_margin = 40,
661 .right_margin = 88,
662 .upper_margin = 33,
663 .lower_margin = 10,
664 .hsync_len = 128,
665 .vsync_len = 2,
666 .sync = 0,
667 .vmode = FB_VMODE_NONINTERLACED
668 } }, {
669 .bus = -1,
670 .addr = 0,
671 .pixfmt = IPU_PIX_FMT_LVDS666,
672 .detect = detect_i2c,
673 .enable = enable_lvds,
674 .mode = {
675 .name = "wsvga-lvds",
676 .refresh = 60,
677 .xres = 1024,
678 .yres = 600,
679 .pixclock = 15385,
680 .left_margin = 220,
681 .right_margin = 40,
682 .upper_margin = 21,
683 .lower_margin = 7,
684 .hsync_len = 60,
685 .vsync_len = 10,
686 .sync = FB_SYNC_EXT,
687 .vmode = FB_VMODE_NONINTERLACED
688 } } };
689 size_t display_count = ARRAY_SIZE(displays);
690
691 static void setup_display(void)
692 {
693 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
694 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
695 int reg;
696
697 enable_ipu_clock();
698 imx_setup_hdmi();
699 /* Turn on LDB0,IPU,IPU DI0 clocks */
700 reg = __raw_readl(&mxc_ccm->CCGR3);
701 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
702 writel(reg, &mxc_ccm->CCGR3);
703
704 /* set LDB0, LDB1 clk select to 011/011 */
705 reg = readl(&mxc_ccm->cs2cdr);
706 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
707 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
708 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
709 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
710 writel(reg, &mxc_ccm->cs2cdr);
711
712 reg = readl(&mxc_ccm->cscmr2);
713 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
714 writel(reg, &mxc_ccm->cscmr2);
715
716 reg = readl(&mxc_ccm->chsccdr);
717 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
718 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
719 writel(reg, &mxc_ccm->chsccdr);
720
721 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
722 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
723 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
724 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
725 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
726 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
727 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
728 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
729 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
730 writel(reg, &iomux->gpr[2]);
731
732 reg = readl(&iomux->gpr[3]);
733 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
734 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
735 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
736 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
737 writel(reg, &iomux->gpr[3]);
738
739 /* backlight unconditionally on for now */
740 imx_iomux_v3_setup_multiple_pads(backlight_pads,
741 ARRAY_SIZE(backlight_pads));
742 /* use 0 for EDT 7", use 1 for LG fullHD panel */
743 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
744 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
745 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
746 }
747 #endif /* defined(CONFIG_VIDEO_IPUV3) */
748
749 int board_early_init_f(void)
750 {
751 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
752 ARRAY_SIZE(pwr_intb_pads));
753 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
754 setup_iomux_dte_uart();
755 #else
756 setup_iomux_dce_uart();
757 #endif
758
759 #if defined(CONFIG_VIDEO_IPUV3)
760 setup_display();
761 #endif
762 return 0;
763 }
764
765 /*
766 * Do not overwrite the console
767 * Use always serial for U-Boot console
768 */
769 int overwrite_console(void)
770 {
771 return 1;
772 }
773
774 int board_init(void)
775 {
776 /* address of boot parameters */
777 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
778
779 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
780 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
781 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
782
783 #ifdef CONFIG_TDX_CMD_IMX_MFGR
784 (void) pmic_init();
785 #endif
786
787 #ifdef CONFIG_SATA
788 setup_sata();
789 #endif
790
791 setup_iomux_gpio();
792
793 return 0;
794 }
795
796 #ifdef CONFIG_BOARD_LATE_INIT
797 int board_late_init(void)
798 {
799 #if defined(CONFIG_REVISION_TAG) && \
800 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
801 char env_str[256];
802 u32 rev;
803
804 rev = get_board_rev();
805 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
806 setenv("board_rev", env_str);
807
808 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
809 if ((rev & 0xfff0) == 0x0100) {
810 char *fdt_env;
811
812 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
813 setup_iomux_dce_uart();
814
815 /* if using the default device tree, use version for V1.0 HW */
816 fdt_env = getenv("fdt_file");
817 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
818 setenv("fdt_file", FDT_FILE_V1_0);
819 printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
820 #ifndef CONFIG_ENV_IS_NOWHERE
821 saveenv();
822 #endif
823 }
824 }
825 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
826 #endif /* CONFIG_REVISION_TAG */
827
828 return 0;
829 }
830 #endif /* CONFIG_BOARD_LATE_INIT */
831
832 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
833 int ft_system_setup(void *blob, bd_t *bd)
834 {
835 return 0;
836 }
837 #endif
838
839 int checkboard(void)
840 {
841 char it[] = " IT";
842 int minc, maxc;
843
844 switch (get_cpu_temp_grade(&minc, &maxc)) {
845 case TEMP_AUTOMOTIVE:
846 case TEMP_INDUSTRIAL:
847 break;
848 case TEMP_EXTCOMMERCIAL:
849 default:
850 it[0] = 0;
851 };
852 printf("Model: Toradex Apalis iMX6 %s %s%s\n",
853 is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
854 (gd->ram_size == 0x80000000) ? "2GB" :
855 (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
856 return 0;
857 }
858
859 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
860 int ft_board_setup(void *blob, bd_t *bd)
861 {
862 return ft_common_board_setup(blob, bd);
863 }
864 #endif
865
866 #ifdef CONFIG_CMD_BMODE
867 static const struct boot_mode board_boot_modes[] = {
868 /* 4-bit bus width */
869 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
870 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
871 {NULL, 0},
872 };
873 #endif
874
875 int misc_init_r(void)
876 {
877 #ifdef CONFIG_CMD_BMODE
878 add_board_boot_modes(board_boot_modes);
879 #endif
880 return 0;
881 }
882
883 #ifdef CONFIG_LDO_BYPASS_CHECK
884 /* TODO, use external pmic, for now always ldo_enable */
885 void ldo_mode_set(int ldo_bypass)
886 {
887 return;
888 }
889 #endif
890
891 #ifdef CONFIG_SPL_BUILD
892 #include <spl.h>
893 #include <libfdt.h>
894 #include "asm/arch/mx6q-ddr.h"
895 #include "asm/arch/iomux.h"
896 #include "asm/arch/crm_regs.h"
897
898 static int mx6_com_dcd_table[] = {
899 /* ddr-setup.cfg */
900 MX6_IOM_DRAM_SDQS0, 0x00000030,
901 MX6_IOM_DRAM_SDQS1, 0x00000030,
902 MX6_IOM_DRAM_SDQS2, 0x00000030,
903 MX6_IOM_DRAM_SDQS3, 0x00000030,
904 MX6_IOM_DRAM_SDQS4, 0x00000030,
905 MX6_IOM_DRAM_SDQS5, 0x00000030,
906 MX6_IOM_DRAM_SDQS6, 0x00000030,
907 MX6_IOM_DRAM_SDQS7, 0x00000030,
908
909 MX6_IOM_GRP_B0DS, 0x00000030,
910 MX6_IOM_GRP_B1DS, 0x00000030,
911 MX6_IOM_GRP_B2DS, 0x00000030,
912 MX6_IOM_GRP_B3DS, 0x00000030,
913 MX6_IOM_GRP_B4DS, 0x00000030,
914 MX6_IOM_GRP_B5DS, 0x00000030,
915 MX6_IOM_GRP_B6DS, 0x00000030,
916 MX6_IOM_GRP_B7DS, 0x00000030,
917 MX6_IOM_GRP_ADDDS, 0x00000030,
918 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
919 MX6_IOM_GRP_CTLDS, 0x00000030,
920
921 MX6_IOM_DRAM_DQM0, 0x00020030,
922 MX6_IOM_DRAM_DQM1, 0x00020030,
923 MX6_IOM_DRAM_DQM2, 0x00020030,
924 MX6_IOM_DRAM_DQM3, 0x00020030,
925 MX6_IOM_DRAM_DQM4, 0x00020030,
926 MX6_IOM_DRAM_DQM5, 0x00020030,
927 MX6_IOM_DRAM_DQM6, 0x00020030,
928 MX6_IOM_DRAM_DQM7, 0x00020030,
929
930 MX6_IOM_DRAM_CAS, 0x00020030,
931 MX6_IOM_DRAM_RAS, 0x00020030,
932 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
933 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
934
935 MX6_IOM_DRAM_RESET, 0x00020030,
936 MX6_IOM_DRAM_SDCKE0, 0x00003000,
937 MX6_IOM_DRAM_SDCKE1, 0x00003000,
938
939 MX6_IOM_DRAM_SDODT0, 0x00003030,
940 MX6_IOM_DRAM_SDODT1, 0x00003030,
941
942 /* (differential input) */
943 MX6_IOM_DDRMODE_CTL, 0x00020000,
944 /* (differential input) */
945 MX6_IOM_GRP_DDRMODE, 0x00020000,
946 /* disable ddr pullups */
947 MX6_IOM_GRP_DDRPKE, 0x00000000,
948 MX6_IOM_DRAM_SDBA2, 0x00000000,
949 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
950 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
951
952 /* Read data DQ Byte0-3 delay */
953 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
954 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
955 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
956 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
957 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
958 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
959 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
960 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
961
962 /*
963 * MDMISC mirroring interleaved (row/bank/col)
964 */
965 MX6_MMDC_P0_MDMISC, 0x00081740,
966
967 /*
968 * MDSCR con_req
969 */
970 MX6_MMDC_P0_MDSCR, 0x00008000,
971
972 /* 1066mhz_4x128mx16.cfg */
973
974 MX6_MMDC_P0_MDPDC, 0x00020036,
975 MX6_MMDC_P0_MDCFG0, 0x555A7954,
976 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
977 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
978 MX6_MMDC_P0_MDRWD, 0x000026D2,
979 MX6_MMDC_P0_MDOR, 0x005A1023,
980 MX6_MMDC_P0_MDOTC, 0x09555050,
981 MX6_MMDC_P0_MDPDC, 0x00025576,
982 MX6_MMDC_P0_MDASP, 0x00000027,
983 MX6_MMDC_P0_MDCTL, 0x831A0000,
984 MX6_MMDC_P0_MDSCR, 0x04088032,
985 MX6_MMDC_P0_MDSCR, 0x00008033,
986 MX6_MMDC_P0_MDSCR, 0x00428031,
987 MX6_MMDC_P0_MDSCR, 0x19308030,
988 MX6_MMDC_P0_MDSCR, 0x04008040,
989 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
990 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
991 MX6_MMDC_P0_MDREF, 0x00005800,
992 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
993 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
994
995 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
996 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
997 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
998 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
999
1000 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
1001 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
1002
1003 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
1004 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
1005
1006 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1007 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1008 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1009 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1010
1011 MX6_MMDC_P0_MPMUR0, 0x00000800,
1012 MX6_MMDC_P1_MPMUR0, 0x00000800,
1013 MX6_MMDC_P0_MDSCR, 0x00000000,
1014 MX6_MMDC_P0_MAPSR, 0x00011006,
1015 };
1016
1017 static int mx6_it_dcd_table[] = {
1018 /* ddr-setup.cfg */
1019 MX6_IOM_DRAM_SDQS0, 0x00000030,
1020 MX6_IOM_DRAM_SDQS1, 0x00000030,
1021 MX6_IOM_DRAM_SDQS2, 0x00000030,
1022 MX6_IOM_DRAM_SDQS3, 0x00000030,
1023 MX6_IOM_DRAM_SDQS4, 0x00000030,
1024 MX6_IOM_DRAM_SDQS5, 0x00000030,
1025 MX6_IOM_DRAM_SDQS6, 0x00000030,
1026 MX6_IOM_DRAM_SDQS7, 0x00000030,
1027
1028 MX6_IOM_GRP_B0DS, 0x00000030,
1029 MX6_IOM_GRP_B1DS, 0x00000030,
1030 MX6_IOM_GRP_B2DS, 0x00000030,
1031 MX6_IOM_GRP_B3DS, 0x00000030,
1032 MX6_IOM_GRP_B4DS, 0x00000030,
1033 MX6_IOM_GRP_B5DS, 0x00000030,
1034 MX6_IOM_GRP_B6DS, 0x00000030,
1035 MX6_IOM_GRP_B7DS, 0x00000030,
1036 MX6_IOM_GRP_ADDDS, 0x00000030,
1037 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1038 MX6_IOM_GRP_CTLDS, 0x00000030,
1039
1040 MX6_IOM_DRAM_DQM0, 0x00020030,
1041 MX6_IOM_DRAM_DQM1, 0x00020030,
1042 MX6_IOM_DRAM_DQM2, 0x00020030,
1043 MX6_IOM_DRAM_DQM3, 0x00020030,
1044 MX6_IOM_DRAM_DQM4, 0x00020030,
1045 MX6_IOM_DRAM_DQM5, 0x00020030,
1046 MX6_IOM_DRAM_DQM6, 0x00020030,
1047 MX6_IOM_DRAM_DQM7, 0x00020030,
1048
1049 MX6_IOM_DRAM_CAS, 0x00020030,
1050 MX6_IOM_DRAM_RAS, 0x00020030,
1051 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
1052 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
1053
1054 MX6_IOM_DRAM_RESET, 0x00020030,
1055 MX6_IOM_DRAM_SDCKE0, 0x00003000,
1056 MX6_IOM_DRAM_SDCKE1, 0x00003000,
1057
1058 MX6_IOM_DRAM_SDODT0, 0x00003030,
1059 MX6_IOM_DRAM_SDODT1, 0x00003030,
1060
1061 /* (differential input) */
1062 MX6_IOM_DDRMODE_CTL, 0x00020000,
1063 /* (differential input) */
1064 MX6_IOM_GRP_DDRMODE, 0x00020000,
1065 /* disable ddr pullups */
1066 MX6_IOM_GRP_DDRPKE, 0x00000000,
1067 MX6_IOM_DRAM_SDBA2, 0x00000000,
1068 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1069 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
1070
1071 /* Read data DQ Byte0-3 delay */
1072 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
1073 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
1074 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
1075 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
1076 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
1077 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
1078 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
1079 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
1080
1081 /*
1082 * MDMISC mirroring interleaved (row/bank/col)
1083 */
1084 MX6_MMDC_P0_MDMISC, 0x00081740,
1085
1086 /*
1087 * MDSCR con_req
1088 */
1089 MX6_MMDC_P0_MDSCR, 0x00008000,
1090
1091 /* 1066mhz_4x256mx16.cfg */
1092
1093 MX6_MMDC_P0_MDPDC, 0x00020036,
1094 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1095 MX6_MMDC_P0_MDCFG1, 0xff328f64,
1096 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1097 MX6_MMDC_P0_MDRWD, 0x000026D2,
1098 MX6_MMDC_P0_MDOR, 0x008E1023,
1099 MX6_MMDC_P0_MDOTC, 0x09444040,
1100 MX6_MMDC_P0_MDPDC, 0x00025576,
1101 MX6_MMDC_P0_MDASP, 0x00000047,
1102 MX6_MMDC_P0_MDCTL, 0x841A0000,
1103 MX6_MMDC_P0_MDSCR, 0x02888032,
1104 MX6_MMDC_P0_MDSCR, 0x00008033,
1105 MX6_MMDC_P0_MDSCR, 0x00048031,
1106 MX6_MMDC_P0_MDSCR, 0x19408030,
1107 MX6_MMDC_P0_MDSCR, 0x04008040,
1108 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1109 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1110 MX6_MMDC_P0_MDREF, 0x00007800,
1111 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1112 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1113
1114 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1115 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1116 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1117 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1118
1119 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1120 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1121
1122 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1123 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1124
1125 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1126 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1127 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1128 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1129
1130 MX6_MMDC_P0_MPMUR0, 0x00000800,
1131 MX6_MMDC_P1_MPMUR0, 0x00000800,
1132 MX6_MMDC_P0_MDSCR, 0x00000000,
1133 MX6_MMDC_P0_MAPSR, 0x00011006,
1134 };
1135
1136
1137 static void ccgr_init(void)
1138 {
1139 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1140
1141 writel(0x00C03F3F, &ccm->CCGR0);
1142 writel(0x0030FC03, &ccm->CCGR1);
1143 writel(0x0FFFFFF3, &ccm->CCGR2);
1144 writel(0x3FF0300F, &ccm->CCGR3);
1145 writel(0x00FFF300, &ccm->CCGR4);
1146 writel(0x0F0000F3, &ccm->CCGR5);
1147 writel(0x000003FF, &ccm->CCGR6);
1148
1149 /*
1150 * Setup CCM_CCOSR register as follows:
1151 *
1152 * cko1_en = 1 --> CKO1 enabled
1153 * cko1_div = 111 --> divide by 8
1154 * cko1_sel = 1011 --> ahb_clk_root
1155 *
1156 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1157 */
1158 writel(0x000000FB, &ccm->ccosr);
1159 }
1160
1161 static void gpr_init(void)
1162 {
1163 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
1164
1165 /* enable AXI cache for VDOA/VPU/IPU */
1166 writel(0xF00000CF, &iomux->gpr[4]);
1167 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
1168 writel(0x007F007F, &iomux->gpr[6]);
1169 writel(0x007F007F, &iomux->gpr[7]);
1170 }
1171
1172 static void ddr_init(int *table, int size)
1173 {
1174 int i;
1175
1176 for (i = 0; i < size / 2 ; i++)
1177 writel(table[2 * i + 1], table[2 * i]);
1178 }
1179
1180 static void spl_dram_init(void)
1181 {
1182 int minc, maxc;
1183
1184 switch (get_cpu_temp_grade(&minc, &maxc)) {
1185 case TEMP_COMMERCIAL:
1186 case TEMP_EXTCOMMERCIAL:
1187 puts("Commercial temperature grade DDR3 timings.\n");
1188 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1189 break;
1190 case TEMP_INDUSTRIAL:
1191 case TEMP_AUTOMOTIVE:
1192 default:
1193 puts("Industrial temperature grade DDR3 timings.\n");
1194 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1195 break;
1196 };
1197 udelay(100);
1198 }
1199
1200 void board_init_f(ulong dummy)
1201 {
1202 /* setup AIPS and disable watchdog */
1203 arch_cpu_init();
1204
1205 ccgr_init();
1206 gpr_init();
1207
1208 /* iomux and setup of i2c */
1209 board_early_init_f();
1210
1211 /* setup GP timer */
1212 timer_init();
1213
1214 /* UART clocks enabled and gd valid - init serial console */
1215 preloader_console_init();
1216
1217 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1218 /* Make sure we use dte mode */
1219 setup_dtemode_uart();
1220 #endif
1221
1222 /* DDR initialization */
1223 spl_dram_init();
1224
1225 /* Clear the BSS. */
1226 memset(__bss_start, 0, __bss_end - __bss_start);
1227
1228 /* load/boot image from boot device */
1229 board_init_r(NULL, 0);
1230 }
1231
1232 void reset_cpu(ulong addr)
1233 {
1234 }
1235
1236 #endif
1237
1238 static struct mxc_serial_platdata mxc_serial_plat = {
1239 .reg = (struct mxc_uart *)UART1_BASE,
1240 .use_dte = true,
1241 };
1242
1243 U_BOOT_DEVICE(mxc_serial) = {
1244 .name = "serial_mxc",
1245 .platdata = &mxc_serial_plat,
1246 };
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