]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/toradex/colibri_imx6/colibri_imx6.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
imx: imx6: Move gpr_init() function to soc.c
[people/ms/u-boot.git] / board / toradex / colibri_imx6 / colibri_imx6.c
1 /*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4 * Copyright (C) 2014-2016, Toradex AG
5 * copied from nitrogen6x
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/mx6-ddr.h>
18 #include <asm/arch/mxc_hdmi.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/bootm.h>
21 #include <asm/gpio.h>
22 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/mach-imx/mxc_i2c.h>
24 #include <asm/mach-imx/sata.h>
25 #include <asm/mach-imx/boot_mode.h>
26 #include <asm/mach-imx/video.h>
27 #include <asm/io.h>
28 #include <dm/platform_data/serial_mxc.h>
29 #include <dm/platdata.h>
30 #include <fsl_esdhc.h>
31 #include <g_dnl.h>
32 #include <i2c.h>
33 #include <imx_thermal.h>
34 #include <linux/errno.h>
35 #include <malloc.h>
36 #include <micrel.h>
37 #include <miiphy.h>
38 #include <mmc.h>
39 #include <netdev.h>
40
41 #include "../common/tdx-cfg-block.h"
42 #ifdef CONFIG_TDX_CMD_IMX_MFGR
43 #include "pf0100.h"
44 #endif
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
50 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51
52 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
53 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
54 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
55
56 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
58
59 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
61
62 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
64
65 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
66 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
67 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
68
69 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
70 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
71 PAD_CTL_SRE_SLOW)
72
73 #define NO_PULLUP ( \
74 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
75 PAD_CTL_SRE_SLOW)
76
77 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
78 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
79 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
80
81 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
82
83 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
84
85 int dram_init(void)
86 {
87 /* use the DDR controllers configured size */
88 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
89 (ulong)imx_ddr_size());
90
91 return 0;
92 }
93
94 /* Colibri UARTA */
95 iomux_v3_cfg_t const uart1_pads[] = {
96 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
97 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
98 };
99
100 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
101 /* Colibri I2C */
102 struct i2c_pads_info i2c_pad_info1 = {
103 .scl = {
104 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
105 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
106 .gp = IMX_GPIO_NR(1, 3)
107 },
108 .sda = {
109 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
110 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
111 .gp = IMX_GPIO_NR(1, 6)
112 }
113 };
114
115 /* Colibri local, PMIC, SGTL5000, STMPE811 */
116 struct i2c_pads_info i2c_pad_info_loc = {
117 .scl = {
118 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
119 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
120 .gp = IMX_GPIO_NR(2, 30)
121 },
122 .sda = {
123 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
124 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
125 .gp = IMX_GPIO_NR(3, 16)
126 }
127 };
128
129 /* Apalis MMC */
130 iomux_v3_cfg_t const usdhc1_pads[] = {
131 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
138 # define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
139 };
140
141 /* eMMC */
142 iomux_v3_cfg_t const usdhc3_pads[] = {
143 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 };
155
156 iomux_v3_cfg_t const enet_pads[] = {
157 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
158 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
159 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
161 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
162 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
163 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
164 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 };
168
169 static void setup_iomux_enet(void)
170 {
171 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
172 }
173
174 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
175 iomux_v3_cfg_t const gpio_pads[] = {
176 /* ADDRESS[17:18] [25] used as GPIO */
177 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
178 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
179 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP),
180 /* ADDRESS[19:24] used as GPIO */
181 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
182 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
183 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
184 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
185 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
186 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
187 /* DATA[16:29] [31] used as GPIO */
188 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),
189 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP),
190 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
191 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
192 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
193 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
194 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP),
195 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
196 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
197 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
198 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),
199 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
200 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
201 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
202 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
203 /* DQM[0:3] used as GPIO */
204 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP),
205 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP),
206 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
207 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP),
208 /* RDY used as GPIO */
209 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP),
210 /* ADDRESS[16] DATA[30] used as GPIO */
211 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN),
212 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
213 /* CSI pins used as GPIO */
214 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
215 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
216 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
217 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
218 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),
219 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN),
220 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
221 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
222 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),
223 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),
224 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP),
225 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
226 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
227 /* GPIO */
228 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP),
229 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),
230 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
231 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP),
232 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),
233 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),
234 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
235 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
236 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
237 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
238 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
239 /* USBH_OC */
240 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
241 /* USBC_ID */
242 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
243 /* USBC_DET */
244 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
245 };
246
247 static void setup_iomux_gpio(void)
248 {
249 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
250 }
251
252 iomux_v3_cfg_t const usb_pads[] = {
253 /* USB_PE */
254 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
255 # define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
256 };
257
258 /*
259 * UARTs are used in DTE mode, switch the mode on all UARTs before
260 * any pinmuxing connects a (DCE) output to a transceiver output.
261 */
262 #define UFCR 0x90 /* FIFO Control Register */
263 #define UFCR_DCEDTE (1<<6) /* DCE=0 */
264
265 static void setup_dtemode_uart(void)
266 {
267 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
268 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
269 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
270 }
271
272 static void setup_iomux_uart(void)
273 {
274 setup_dtemode_uart();
275 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
276 }
277
278 #ifdef CONFIG_USB_EHCI_MX6
279 int board_ehci_hcd_init(int port)
280 {
281 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
282 return 0;
283 }
284
285 int board_ehci_power(int port, int on)
286 {
287 switch (port) {
288 case 0:
289 /* control OTG power */
290 /* No special PE for USBC, always on when ID pin signals
291 host mode */
292 break;
293 case 1:
294 /* Control MXM USBH */
295 /* Set MXM USBH power enable, '0' means on */
296 gpio_direction_output(GPIO_USBH_EN, !on);
297 mdelay(100);
298 break;
299 default:
300 break;
301 }
302 return 0;
303 }
304 #endif
305
306 #ifdef CONFIG_FSL_ESDHC
307 /* use the following sequence: eMMC, MMC */
308 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
309 {USDHC3_BASE_ADDR},
310 {USDHC1_BASE_ADDR},
311 };
312
313 int board_mmc_getcd(struct mmc *mmc)
314 {
315 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
316 int ret = true; /* default: assume inserted */
317
318 switch (cfg->esdhc_base) {
319 case USDHC1_BASE_ADDR:
320 gpio_direction_input(GPIO_MMC_CD);
321 ret = !gpio_get_value(GPIO_MMC_CD);
322 break;
323 }
324
325 return ret;
326 }
327
328 int board_mmc_init(bd_t *bis)
329 {
330 #ifndef CONFIG_SPL_BUILD
331 s32 status = 0;
332 u32 index = 0;
333
334 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
335 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
336
337 usdhc_cfg[0].max_bus_width = 8;
338 usdhc_cfg[1].max_bus_width = 4;
339
340 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
341 switch (index) {
342 case 0:
343 imx_iomux_v3_setup_multiple_pads(
344 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
345 break;
346 case 1:
347 imx_iomux_v3_setup_multiple_pads(
348 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
349 break;
350 default:
351 printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
352 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
353 return status;
354 }
355
356 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
357 }
358
359 return status;
360 #else
361 struct src *psrc = (struct src *)SRC_BASE_ADDR;
362 unsigned reg = readl(&psrc->sbmr1) >> 11;
363 /*
364 * Upon reading BOOT_CFG register the following map is done:
365 * Bit 11 and 12 of BOOT_CFG register can determine the current
366 * mmc port
367 * 0x1 SD1
368 * 0x2 SD2
369 * 0x3 SD4
370 */
371
372 switch (reg & 0x3) {
373 case 0x0:
374 imx_iomux_v3_setup_multiple_pads(
375 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
376 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
377 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
378 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
379 break;
380 case 0x2:
381 imx_iomux_v3_setup_multiple_pads(
382 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
383 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
384 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
385 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
386 break;
387 default:
388 puts("MMC boot device not available");
389 }
390
391 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
392 #endif
393 }
394 #endif
395
396 int board_phy_config(struct phy_device *phydev)
397 {
398 if (phydev->drv->config)
399 phydev->drv->config(phydev);
400
401 return 0;
402 }
403
404 int board_eth_init(bd_t *bis)
405 {
406 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
407 uint32_t base = IMX_FEC_BASE;
408 struct mii_dev *bus = NULL;
409 struct phy_device *phydev = NULL;
410 int ret;
411
412 /* provide the PHY clock from the i.MX 6 */
413 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
414 if (ret)
415 return ret;
416 /* set gpr1[ENET_CLK_SEL] */
417 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
418
419 setup_iomux_enet();
420
421 #ifdef CONFIG_FEC_MXC
422 bus = fec_get_miibus(base, -1);
423 if (!bus)
424 return 0;
425 /* scan PHY 1..7 */
426 phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
427 if (!phydev) {
428 free(bus);
429 puts("no PHY found\n");
430 return 0;
431 }
432 phy_reset(phydev);
433 printf("using PHY at %d\n", phydev->addr);
434 ret = fec_probe(bis, -1, base, bus, phydev);
435 if (ret) {
436 printf("FEC MXC: %s:failed\n", __func__);
437 free(phydev);
438 free(bus);
439 }
440 #endif
441 return 0;
442 }
443
444 static iomux_v3_cfg_t const pwr_intb_pads[] = {
445 /*
446 * the bootrom sets the iomux to vselect, potentially connecting
447 * two outputs. Set this back to GPIO
448 */
449 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
450 };
451
452 #if defined(CONFIG_VIDEO_IPUV3)
453
454 static iomux_v3_cfg_t const backlight_pads[] = {
455 /* Backlight On */
456 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
457 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
458 /* Backlight PWM, used as GPIO in U-Boot */
459 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
460 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
461 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
462 };
463
464 static iomux_v3_cfg_t const rgb_pads[] = {
465 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
466 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
467 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
468 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
469 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
470 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
471 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
472 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
473 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
474 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
475 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
476 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
477 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
478 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
479 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
480 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
481 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
482 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
483 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
484 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
485 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
486 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
487 };
488
489 static void do_enable_hdmi(struct display_info_t const *dev)
490 {
491 imx_enable_hdmi_phy();
492 }
493
494 static void enable_rgb(struct display_info_t const *dev)
495 {
496 imx_iomux_v3_setup_multiple_pads(
497 rgb_pads,
498 ARRAY_SIZE(rgb_pads));
499 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
500 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
501 }
502
503 static int detect_default(struct display_info_t const *dev)
504 {
505 (void) dev;
506 return 1;
507 }
508
509 struct display_info_t const displays[] = {{
510 .bus = -1,
511 .addr = 0,
512 .pixfmt = IPU_PIX_FMT_RGB24,
513 .detect = detect_hdmi,
514 .enable = do_enable_hdmi,
515 .mode = {
516 .name = "HDMI",
517 .refresh = 60,
518 .xres = 1024,
519 .yres = 768,
520 .pixclock = 15385,
521 .left_margin = 220,
522 .right_margin = 40,
523 .upper_margin = 21,
524 .lower_margin = 7,
525 .hsync_len = 60,
526 .vsync_len = 10,
527 .sync = FB_SYNC_EXT,
528 .vmode = FB_VMODE_NONINTERLACED
529 } }, {
530 .bus = -1,
531 .addr = 0,
532 .pixfmt = IPU_PIX_FMT_RGB666,
533 .detect = detect_default,
534 .enable = enable_rgb,
535 .mode = {
536 .name = "vga-rgb",
537 .refresh = 60,
538 .xres = 640,
539 .yres = 480,
540 .pixclock = 33000,
541 .left_margin = 48,
542 .right_margin = 16,
543 .upper_margin = 31,
544 .lower_margin = 11,
545 .hsync_len = 96,
546 .vsync_len = 2,
547 .sync = 0,
548 .vmode = FB_VMODE_NONINTERLACED
549 } }, {
550 .bus = -1,
551 .addr = 0,
552 .pixfmt = IPU_PIX_FMT_RGB666,
553 .enable = enable_rgb,
554 .mode = {
555 .name = "wvga-rgb",
556 .refresh = 60,
557 .xres = 800,
558 .yres = 480,
559 .pixclock = 25000,
560 .left_margin = 40,
561 .right_margin = 88,
562 .upper_margin = 33,
563 .lower_margin = 10,
564 .hsync_len = 128,
565 .vsync_len = 2,
566 .sync = 0,
567 .vmode = FB_VMODE_NONINTERLACED
568 } } };
569 size_t display_count = ARRAY_SIZE(displays);
570
571 static void setup_display(void)
572 {
573 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
574 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
575 int reg;
576
577 enable_ipu_clock();
578 imx_setup_hdmi();
579 /* Turn on LDB0,IPU,IPU DI0 clocks */
580 reg = __raw_readl(&mxc_ccm->CCGR3);
581 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
582 writel(reg, &mxc_ccm->CCGR3);
583
584 /* set LDB0, LDB1 clk select to 011/011 */
585 reg = readl(&mxc_ccm->cs2cdr);
586 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
587 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
588 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
589 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
590 writel(reg, &mxc_ccm->cs2cdr);
591
592 reg = readl(&mxc_ccm->cscmr2);
593 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
594 writel(reg, &mxc_ccm->cscmr2);
595
596 reg = readl(&mxc_ccm->chsccdr);
597 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
598 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
599 writel(reg, &mxc_ccm->chsccdr);
600
601 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
602 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
603 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
604 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
605 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
606 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
607 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
608 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
609 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
610 writel(reg, &iomux->gpr[2]);
611
612 reg = readl(&iomux->gpr[3]);
613 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
614 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
615 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
616 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
617 writel(reg, &iomux->gpr[3]);
618
619 /* backlight unconditionally on for now */
620 imx_iomux_v3_setup_multiple_pads(backlight_pads,
621 ARRAY_SIZE(backlight_pads));
622 /* use 0 for EDT 7", use 1 for LG fullHD panel */
623 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
624 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
625 }
626 #endif /* defined(CONFIG_VIDEO_IPUV3) */
627
628 int board_early_init_f(void)
629 {
630 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
631 ARRAY_SIZE(pwr_intb_pads));
632 setup_iomux_uart();
633
634 #if defined(CONFIG_VIDEO_IPUV3)
635 setup_display();
636 #endif
637 return 0;
638 }
639
640 /*
641 * Do not overwrite the console
642 * Use always serial for U-Boot console
643 */
644 int overwrite_console(void)
645 {
646 return 1;
647 }
648
649 int board_init(void)
650 {
651 /* address of boot parameters */
652 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
653
654 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
655 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
656
657 #ifdef CONFIG_TDX_CMD_IMX_MFGR
658 (void) pmic_init();
659 #endif
660
661 #ifdef CONFIG_SATA
662 setup_sata();
663 #endif
664
665 setup_iomux_gpio();
666
667 return 0;
668 }
669
670 #ifdef CONFIG_BOARD_LATE_INIT
671 int board_late_init(void)
672 {
673 #if defined(CONFIG_REVISION_TAG) && \
674 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
675 char env_str[256];
676 u32 rev;
677
678 rev = get_board_rev();
679 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
680 env_set("board_rev", env_str);
681 #endif
682
683 return 0;
684 }
685 #endif /* CONFIG_BOARD_LATE_INIT */
686
687 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
688 int ft_system_setup(void *blob, bd_t *bd)
689 {
690 return 0;
691 }
692 #endif
693
694 int checkboard(void)
695 {
696 char it[] = " IT";
697 int minc, maxc;
698
699 switch (get_cpu_temp_grade(&minc, &maxc)) {
700 case TEMP_AUTOMOTIVE:
701 case TEMP_INDUSTRIAL:
702 break;
703 case TEMP_EXTCOMMERCIAL:
704 default:
705 it[0] = 0;
706 };
707 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
708 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
709 (gd->ram_size == 0x20000000) ? "512" : "256", it);
710 return 0;
711 }
712
713 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
714 int ft_board_setup(void *blob, bd_t *bd)
715 {
716 return ft_common_board_setup(blob, bd);
717 }
718 #endif
719
720 #ifdef CONFIG_CMD_BMODE
721 static const struct boot_mode board_boot_modes[] = {
722 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
723 {NULL, 0},
724 };
725 #endif
726
727 int misc_init_r(void)
728 {
729 #ifdef CONFIG_CMD_BMODE
730 add_board_boot_modes(board_boot_modes);
731 #endif
732 return 0;
733 }
734
735 #ifdef CONFIG_LDO_BYPASS_CHECK
736 /* TODO, use external pmic, for now always ldo_enable */
737 void ldo_mode_set(int ldo_bypass)
738 {
739 return;
740 }
741 #endif
742
743 #ifdef CONFIG_SPL_BUILD
744 #include <spl.h>
745 #include <libfdt.h>
746 #include "asm/arch/mx6dl-ddr.h"
747 #include "asm/arch/iomux.h"
748 #include "asm/arch/crm_regs.h"
749
750 static int mx6s_dcd_table[] = {
751 /* ddr-setup.cfg */
752
753 MX6_IOM_DRAM_SDQS0, 0x00000030,
754 MX6_IOM_DRAM_SDQS1, 0x00000030,
755 MX6_IOM_DRAM_SDQS2, 0x00000030,
756 MX6_IOM_DRAM_SDQS3, 0x00000030,
757 MX6_IOM_DRAM_SDQS4, 0x00000030,
758 MX6_IOM_DRAM_SDQS5, 0x00000030,
759 MX6_IOM_DRAM_SDQS6, 0x00000030,
760 MX6_IOM_DRAM_SDQS7, 0x00000030,
761
762 MX6_IOM_GRP_B0DS, 0x00000030,
763 MX6_IOM_GRP_B1DS, 0x00000030,
764 MX6_IOM_GRP_B2DS, 0x00000030,
765 MX6_IOM_GRP_B3DS, 0x00000030,
766 MX6_IOM_GRP_B4DS, 0x00000030,
767 MX6_IOM_GRP_B5DS, 0x00000030,
768 MX6_IOM_GRP_B6DS, 0x00000030,
769 MX6_IOM_GRP_B7DS, 0x00000030,
770 MX6_IOM_GRP_ADDDS, 0x00000030,
771 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
772 MX6_IOM_GRP_CTLDS, 0x00000030,
773
774 MX6_IOM_DRAM_DQM0, 0x00020030,
775 MX6_IOM_DRAM_DQM1, 0x00020030,
776 MX6_IOM_DRAM_DQM2, 0x00020030,
777 MX6_IOM_DRAM_DQM3, 0x00020030,
778 MX6_IOM_DRAM_DQM4, 0x00020030,
779 MX6_IOM_DRAM_DQM5, 0x00020030,
780 MX6_IOM_DRAM_DQM6, 0x00020030,
781 MX6_IOM_DRAM_DQM7, 0x00020030,
782
783 MX6_IOM_DRAM_CAS, 0x00020030,
784 MX6_IOM_DRAM_RAS, 0x00020030,
785 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
786 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
787
788 MX6_IOM_DRAM_RESET, 0x00020030,
789 MX6_IOM_DRAM_SDCKE0, 0x00003000,
790 MX6_IOM_DRAM_SDCKE1, 0x00003000,
791
792 MX6_IOM_DRAM_SDODT0, 0x00003030,
793 MX6_IOM_DRAM_SDODT1, 0x00003030,
794
795 /* (differential input) */
796 MX6_IOM_DDRMODE_CTL, 0x00020000,
797 /* (differential input) */
798 MX6_IOM_GRP_DDRMODE, 0x00020000,
799 /* disable ddr pullups */
800 MX6_IOM_GRP_DDRPKE, 0x00000000,
801 MX6_IOM_DRAM_SDBA2, 0x00000000,
802 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
803 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
804
805 /* Read data DQ Byte0-3 delay */
806 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
807 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
808 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
809 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
810 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
811 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
812 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
813 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
814
815 /*
816 * MDMISC mirroring interleaved (row/bank/col)
817 */
818 /* TODO: check what the RALAT field does */
819 MX6_MMDC_P0_MDMISC, 0x00081740,
820
821 /*
822 * MDSCR con_req
823 */
824 MX6_MMDC_P0_MDSCR, 0x00008000,
825
826
827 /* 800mhz_2x64mx16.cfg */
828
829 MX6_MMDC_P0_MDPDC, 0x0002002D,
830 MX6_MMDC_P0_MDCFG0, 0x2C305503,
831 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
832 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
833 MX6_MMDC_P0_MDRWD, 0x000026D2,
834 MX6_MMDC_P0_MDOR, 0x00301023,
835 MX6_MMDC_P0_MDOTC, 0x00333030,
836 MX6_MMDC_P0_MDPDC, 0x0002556D,
837 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
838 MX6_MMDC_P0_MDASP, 0x00000017,
839 /* DDR3 DATA BUS SIZE: 64BIT */
840 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
841 /* DDR3 DATA BUS SIZE: 32BIT */
842 MX6_MMDC_P0_MDCTL, 0x82190000,
843
844 /* Write commands to DDR */
845 /* Load Mode Registers */
846 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
847 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
848 MX6_MMDC_P0_MDSCR, 0x04008032,
849 MX6_MMDC_P0_MDSCR, 0x00008033,
850 MX6_MMDC_P0_MDSCR, 0x00048031,
851 MX6_MMDC_P0_MDSCR, 0x13208030,
852 /* ZQ calibration */
853 MX6_MMDC_P0_MDSCR, 0x04008040,
854
855 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
856 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
857 MX6_MMDC_P0_MDREF, 0x00005800,
858
859 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
860 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
861
862 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
863 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
864 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
865 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
866
867 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
868 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
869 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
870 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
871
872 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
873 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
874 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
875 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
876
877 MX6_MMDC_P0_MPMUR0, 0x00000800,
878 MX6_MMDC_P1_MPMUR0, 0x00000800,
879 MX6_MMDC_P0_MDSCR, 0x00000000,
880 MX6_MMDC_P0_MAPSR, 0x00011006,
881 };
882
883 static int mx6dl_dcd_table[] = {
884 /* ddr-setup.cfg */
885
886 MX6_IOM_DRAM_SDQS0, 0x00000030,
887 MX6_IOM_DRAM_SDQS1, 0x00000030,
888 MX6_IOM_DRAM_SDQS2, 0x00000030,
889 MX6_IOM_DRAM_SDQS3, 0x00000030,
890 MX6_IOM_DRAM_SDQS4, 0x00000030,
891 MX6_IOM_DRAM_SDQS5, 0x00000030,
892 MX6_IOM_DRAM_SDQS6, 0x00000030,
893 MX6_IOM_DRAM_SDQS7, 0x00000030,
894
895 MX6_IOM_GRP_B0DS, 0x00000030,
896 MX6_IOM_GRP_B1DS, 0x00000030,
897 MX6_IOM_GRP_B2DS, 0x00000030,
898 MX6_IOM_GRP_B3DS, 0x00000030,
899 MX6_IOM_GRP_B4DS, 0x00000030,
900 MX6_IOM_GRP_B5DS, 0x00000030,
901 MX6_IOM_GRP_B6DS, 0x00000030,
902 MX6_IOM_GRP_B7DS, 0x00000030,
903 MX6_IOM_GRP_ADDDS, 0x00000030,
904 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
905 MX6_IOM_GRP_CTLDS, 0x00000030,
906
907 MX6_IOM_DRAM_DQM0, 0x00020030,
908 MX6_IOM_DRAM_DQM1, 0x00020030,
909 MX6_IOM_DRAM_DQM2, 0x00020030,
910 MX6_IOM_DRAM_DQM3, 0x00020030,
911 MX6_IOM_DRAM_DQM4, 0x00020030,
912 MX6_IOM_DRAM_DQM5, 0x00020030,
913 MX6_IOM_DRAM_DQM6, 0x00020030,
914 MX6_IOM_DRAM_DQM7, 0x00020030,
915
916 MX6_IOM_DRAM_CAS, 0x00020030,
917 MX6_IOM_DRAM_RAS, 0x00020030,
918 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
919 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
920
921 MX6_IOM_DRAM_RESET, 0x00020030,
922 MX6_IOM_DRAM_SDCKE0, 0x00003000,
923 MX6_IOM_DRAM_SDCKE1, 0x00003000,
924
925 MX6_IOM_DRAM_SDODT0, 0x00003030,
926 MX6_IOM_DRAM_SDODT1, 0x00003030,
927
928 /* (differential input) */
929 MX6_IOM_DDRMODE_CTL, 0x00020000,
930 /* (differential input) */
931 MX6_IOM_GRP_DDRMODE, 0x00020000,
932 /* disable ddr pullups */
933 MX6_IOM_GRP_DDRPKE, 0x00000000,
934 MX6_IOM_DRAM_SDBA2, 0x00000000,
935 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
936 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
937
938 /* Read data DQ Byte0-3 delay */
939 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
940 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
941 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
942 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
943 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
944 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
945 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
946 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
947
948 /*
949 * MDMISC mirroring interleaved (row/bank/col)
950 */
951 /* TODO: check what the RALAT field does */
952 MX6_MMDC_P0_MDMISC, 0x00081740,
953
954 /*
955 * MDSCR con_req
956 */
957 MX6_MMDC_P0_MDSCR, 0x00008000,
958
959
960 /* 800mhz_2x64mx16.cfg */
961
962 MX6_MMDC_P0_MDPDC, 0x0002002D,
963 MX6_MMDC_P0_MDCFG0, 0x2C305503,
964 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
965 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
966 MX6_MMDC_P0_MDRWD, 0x000026D2,
967 MX6_MMDC_P0_MDOR, 0x00301023,
968 MX6_MMDC_P0_MDOTC, 0x00333030,
969 MX6_MMDC_P0_MDPDC, 0x0002556D,
970 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
971 MX6_MMDC_P0_MDASP, 0x00000017,
972 /* DDR3 DATA BUS SIZE: 64BIT */
973 MX6_MMDC_P0_MDCTL, 0x821A0000,
974 /* DDR3 DATA BUS SIZE: 32BIT */
975 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
976
977 /* Write commands to DDR */
978 /* Load Mode Registers */
979 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
980 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
981 MX6_MMDC_P0_MDSCR, 0x04008032,
982 MX6_MMDC_P0_MDSCR, 0x00008033,
983 MX6_MMDC_P0_MDSCR, 0x00048031,
984 MX6_MMDC_P0_MDSCR, 0x13208030,
985 /* ZQ calibration */
986 MX6_MMDC_P0_MDSCR, 0x04008040,
987
988 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
989 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
990 MX6_MMDC_P0_MDREF, 0x00005800,
991
992 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
993 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
994
995 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
996 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
997 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
998 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
999
1000 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
1001 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
1002 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
1003 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
1004
1005 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
1006 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
1007 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
1008 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
1009
1010 MX6_MMDC_P0_MPMUR0, 0x00000800,
1011 MX6_MMDC_P1_MPMUR0, 0x00000800,
1012 MX6_MMDC_P0_MDSCR, 0x00000000,
1013 MX6_MMDC_P0_MAPSR, 0x00011006,
1014 };
1015
1016 static void ccgr_init(void)
1017 {
1018 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1019
1020 writel(0x00C03F3F, &ccm->CCGR0);
1021 writel(0x0030FC03, &ccm->CCGR1);
1022 writel(0x0FFFFFF3, &ccm->CCGR2);
1023 writel(0x3FF0300F, &ccm->CCGR3);
1024 writel(0x00FFF300, &ccm->CCGR4);
1025 writel(0x0F0000F3, &ccm->CCGR5);
1026 writel(0x000003FF, &ccm->CCGR6);
1027
1028 /*
1029 * Setup CCM_CCOSR register as follows:
1030 *
1031 * cko1_en = 1 --> CKO1 enabled
1032 * cko1_div = 111 --> divide by 8
1033 * cko1_sel = 1011 --> ahb_clk_root
1034 *
1035 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1036 */
1037 writel(0x000000FB, &ccm->ccosr);
1038 }
1039
1040 static void ddr_init(int *table, int size)
1041 {
1042 int i;
1043
1044 for (i = 0; i < size / 2 ; i++)
1045 writel(table[2 * i + 1], table[2 * i]);
1046 }
1047
1048 static void spl_dram_init(void)
1049 {
1050 int minc, maxc;
1051
1052 switch (get_cpu_temp_grade(&minc, &maxc)) {
1053 case TEMP_COMMERCIAL:
1054 case TEMP_EXTCOMMERCIAL:
1055 if (is_cpu_type(MXC_CPU_MX6DL)) {
1056 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1057 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1058 } else {
1059 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1060 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1061 }
1062 break;
1063 case TEMP_INDUSTRIAL:
1064 case TEMP_AUTOMOTIVE:
1065 default:
1066 if (is_cpu_type(MXC_CPU_MX6DL)) {
1067 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1068 } else {
1069 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1070 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1071 }
1072 break;
1073 };
1074 udelay(100);
1075 }
1076
1077 void board_init_f(ulong dummy)
1078 {
1079 /* setup AIPS and disable watchdog */
1080 arch_cpu_init();
1081
1082 ccgr_init();
1083 gpr_init();
1084
1085 /* iomux and setup of i2c */
1086 board_early_init_f();
1087
1088 /* setup GP timer */
1089 timer_init();
1090
1091 /* UART clocks enabled and gd valid - init serial console */
1092 preloader_console_init();
1093
1094 /* Make sure we use dte mode */
1095 setup_dtemode_uart();
1096
1097 /* DDR initialization */
1098 spl_dram_init();
1099
1100 /* Clear the BSS. */
1101 memset(__bss_start, 0, __bss_end - __bss_start);
1102
1103 /* load/boot image from boot device */
1104 board_init_r(NULL, 0);
1105 }
1106
1107 void reset_cpu(ulong addr)
1108 {
1109 }
1110
1111 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
1112 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
1113 {
1114 unsigned short usb_pid;
1115
1116 usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff;
1117 put_unaligned(usb_pid, &dev->idProduct);
1118
1119 return 0;
1120 }
1121 #endif
1122
1123 #endif
1124
1125 static struct mxc_serial_platdata mxc_serial_plat = {
1126 .reg = (struct mxc_uart *)UART1_BASE,
1127 .use_dte = true,
1128 };
1129
1130 U_BOOT_DEVICE(mxc_serial) = {
1131 .name = "serial_mxc",
1132 .platdata = &mxc_serial_plat,
1133 };
"Das U-Boot" Source Tree