2 * Copyright 2015 Toradex, Inc.
5 * Copyright 2013 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux-vf610.h>
14 #include <asm/arch/ddrmc-vf610.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
18 #include <fdt_support.h>
19 #include <fsl_esdhc.h>
20 #include <jffs2/load_kernel.h>
28 #include "../common/tdx-common.h"
30 DECLARE_GLOBAL_DATA_PTR
;
32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
33 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
35 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
36 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
38 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
39 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
41 #define USB_PEN_GPIO 83
42 #define USB_CDET_GPIO 102
44 static struct ddrmc_cr_setting colibri_vf_cr_settings
[] = {
46 { DDRMC_CR97_WRLVL_EN
, 97 },
47 { DDRMC_CR98_WRLVL_DL_0(0), 98 },
48 { DDRMC_CR99_WRLVL_DL_1(0), 99 },
49 { DDRMC_CR102_RDLVL_REG_EN
| DDRMC_CR102_RDLVL_GT_REGEN
, 102 },
50 { DDRMC_CR105_RDLVL_DL_0(0), 105 },
51 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
52 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
54 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
55 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
56 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
57 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
58 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
59 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
60 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
61 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
62 { DDRMC_CR123_AXI1_P_ODR_EN
| DDRMC_CR123_AXI1_PRI3_RPRI(1) |
63 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
64 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
65 { DDRMC_CR126_PHY_RDLAT(8), 126 },
66 { DDRMC_CR132_WRLAT_ADJ(5) |
67 DDRMC_CR132_RDLAT_ADJ(6), 132 },
68 { DDRMC_CR137_PHYCTL_DL(2), 137 },
69 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
70 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
71 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
72 DDRMC_CR139_PHY_WRLV_DLL(3) |
73 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
74 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
75 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
76 DDRMC_CR143_RDLV_MXDL(128), 143 },
77 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
78 DDRMC_CR144_PHY_RDLV_DLL(3) |
79 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
80 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
81 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
82 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
83 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
84 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
85 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
87 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
88 DDRMC_CR154_PAD_ZQ_MODE(1) |
89 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
90 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
91 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
92 { DDRMC_CR158_TWR(6), 158 },
93 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
94 DDRMC_CR161_TODTH_WR(2), 161 },
99 static const iomux_v3_cfg_t usb_pads
[] = {
100 VF610_PAD_PTD4__GPIO_83
,
101 VF610_PAD_PTC29__GPIO_102
,
106 static const struct ddr3_jedec_timings timings
= {
109 .cke_inactive
= 200000,
115 .tbst_int_interval
= 0,
157 ddrmc_setup_iomux(NULL
, 0);
159 ddrmc_ctrl_init_ddr3(&timings
, colibri_vf_cr_settings
, NULL
, 1, 2);
160 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM
, PHYS_SDRAM_SIZE
);
165 static void setup_iomux_uart(void)
167 static const iomux_v3_cfg_t uart_pads
[] = {
168 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX
, UART_PAD_CTRL
),
169 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX
, UART_PAD_CTRL
),
170 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX
, UART_PAD_CTRL
),
171 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX
, UART_PAD_CTRL
),
174 imx_iomux_v3_setup_multiple_pads(uart_pads
, ARRAY_SIZE(uart_pads
));
177 static void setup_iomux_enet(void)
179 static const iomux_v3_cfg_t enet0_pads
[] = {
180 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT
, ENET_PAD_CTRL
),
181 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO
, ENET_PAD_CTRL
),
182 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC
, ENET_PAD_CTRL
),
183 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV
, ENET_PAD_CTRL
),
184 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1
, ENET_PAD_CTRL
),
185 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0
, ENET_PAD_CTRL
),
186 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER
, ENET_PAD_CTRL
),
187 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1
, ENET_PAD_CTRL
),
188 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0
, ENET_PAD_CTRL
),
189 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN
, ENET_PAD_CTRL
),
192 imx_iomux_v3_setup_multiple_pads(enet0_pads
, ARRAY_SIZE(enet0_pads
));
195 static void setup_iomux_i2c(void)
197 static const iomux_v3_cfg_t i2c0_pads
[] = {
198 VF610_PAD_PTB14__I2C0_SCL
,
199 VF610_PAD_PTB15__I2C0_SDA
,
202 imx_iomux_v3_setup_multiple_pads(i2c0_pads
, ARRAY_SIZE(i2c0_pads
));
205 #ifdef CONFIG_NAND_VF610_NFC
206 static void setup_iomux_nfc(void)
208 static const iomux_v3_cfg_t nfc_pads
[] = {
209 VF610_PAD_PTD23__NF_IO7
,
210 VF610_PAD_PTD22__NF_IO6
,
211 VF610_PAD_PTD21__NF_IO5
,
212 VF610_PAD_PTD20__NF_IO4
,
213 VF610_PAD_PTD19__NF_IO3
,
214 VF610_PAD_PTD18__NF_IO2
,
215 VF610_PAD_PTD17__NF_IO1
,
216 VF610_PAD_PTD16__NF_IO0
,
217 VF610_PAD_PTB24__NF_WE_B
,
218 VF610_PAD_PTB25__NF_CE0_B
,
219 VF610_PAD_PTB27__NF_RE_B
,
220 VF610_PAD_PTC26__NF_RB_B
,
221 VF610_PAD_PTC27__NF_ALE
,
222 VF610_PAD_PTC28__NF_CLE
225 imx_iomux_v3_setup_multiple_pads(nfc_pads
, ARRAY_SIZE(nfc_pads
));
229 #ifdef CONFIG_FSL_DSPI
230 static void setup_iomux_dspi(void)
232 static const iomux_v3_cfg_t dspi1_pads
[] = {
233 VF610_PAD_PTD5__DSPI1_CS0
,
234 VF610_PAD_PTD6__DSPI1_SIN
,
235 VF610_PAD_PTD7__DSPI1_SOUT
,
236 VF610_PAD_PTD8__DSPI1_SCK
,
239 imx_iomux_v3_setup_multiple_pads(dspi1_pads
, ARRAY_SIZE(dspi1_pads
));
243 #ifdef CONFIG_VYBRID_GPIO
244 static void setup_iomux_gpio(void)
246 static const iomux_v3_cfg_t gpio_pads
[] = {
247 VF610_PAD_PTA17__GPIO_7
,
248 VF610_PAD_PTA20__GPIO_10
,
249 VF610_PAD_PTA21__GPIO_11
,
250 VF610_PAD_PTA30__GPIO_20
,
251 VF610_PAD_PTA31__GPIO_21
,
252 VF610_PAD_PTB0__GPIO_22
,
253 VF610_PAD_PTB1__GPIO_23
,
254 VF610_PAD_PTB6__GPIO_28
,
255 VF610_PAD_PTB7__GPIO_29
,
256 VF610_PAD_PTB8__GPIO_30
,
257 VF610_PAD_PTB9__GPIO_31
,
258 VF610_PAD_PTB12__GPIO_34
,
259 VF610_PAD_PTB13__GPIO_35
,
260 VF610_PAD_PTB16__GPIO_38
,
261 VF610_PAD_PTB17__GPIO_39
,
262 VF610_PAD_PTB18__GPIO_40
,
263 VF610_PAD_PTB21__GPIO_43
,
264 VF610_PAD_PTB22__GPIO_44
,
265 VF610_PAD_PTC0__GPIO_45
,
266 VF610_PAD_PTC1__GPIO_46
,
267 VF610_PAD_PTC2__GPIO_47
,
268 VF610_PAD_PTC3__GPIO_48
,
269 VF610_PAD_PTC4__GPIO_49
,
270 VF610_PAD_PTC5__GPIO_50
,
271 VF610_PAD_PTC6__GPIO_51
,
272 VF610_PAD_PTC7__GPIO_52
,
273 VF610_PAD_PTC8__GPIO_53
,
274 VF610_PAD_PTD31__GPIO_63
,
275 VF610_PAD_PTD30__GPIO_64
,
276 VF610_PAD_PTD29__GPIO_65
,
277 VF610_PAD_PTD28__GPIO_66
,
278 VF610_PAD_PTD27__GPIO_67
,
279 VF610_PAD_PTD26__GPIO_68
,
280 VF610_PAD_PTD25__GPIO_69
,
281 VF610_PAD_PTD24__GPIO_70
,
282 VF610_PAD_PTD9__GPIO_88
,
283 VF610_PAD_PTD10__GPIO_89
,
284 VF610_PAD_PTD11__GPIO_90
,
285 VF610_PAD_PTD12__GPIO_91
,
286 VF610_PAD_PTD13__GPIO_92
,
287 VF610_PAD_PTB23__GPIO_93
,
288 VF610_PAD_PTB26__GPIO_96
,
289 VF610_PAD_PTB28__GPIO_98
,
290 VF610_PAD_PTC30__GPIO_103
,
291 VF610_PAD_PTA7__GPIO_134
,
294 imx_iomux_v3_setup_multiple_pads(gpio_pads
, ARRAY_SIZE(gpio_pads
));
298 #ifdef CONFIG_FSL_ESDHC
299 struct fsl_esdhc_cfg esdhc_cfg
[1] = {
303 int board_mmc_getcd(struct mmc
*mmc
)
305 /* eSDHC1 is always present */
309 int board_mmc_init(bd_t
*bis
)
311 static const iomux_v3_cfg_t esdhc1_pads
[] = {
312 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK
, ESDHC_PAD_CTRL
),
313 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD
, ESDHC_PAD_CTRL
),
314 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0
, ESDHC_PAD_CTRL
),
315 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1
, ESDHC_PAD_CTRL
),
316 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2
, ESDHC_PAD_CTRL
),
317 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3
, ESDHC_PAD_CTRL
),
320 esdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
322 imx_iomux_v3_setup_multiple_pads(
323 esdhc1_pads
, ARRAY_SIZE(esdhc1_pads
));
325 return fsl_esdhc_initialize(bis
, &esdhc_cfg
[0]);
329 static inline int is_colibri_vf61(void)
331 struct mscm
*mscm
= (struct mscm
*)MSCM_BASE_ADDR
;
334 * Detect board type by Level 2 Cache: VF50 don't have any
337 return !!mscm
->cpxcfg1
;
340 static void clock_init(void)
342 struct ccm_reg
*ccm
= (struct ccm_reg
*)CCM_BASE_ADDR
;
343 struct anadig_reg
*anadig
= (struct anadig_reg
*)ANADIG_BASE_ADDR
;
344 u32 pfd_clk_sel
, ddr_clk_sel
;
346 clrsetbits_le32(&ccm
->ccgr0
, CCM_REG_CTRL_MASK
,
347 CCM_CCGR0_UART0_CTRL_MASK
);
348 #ifdef CONFIG_FSL_DSPI
349 setbits_le32(&ccm
->ccgr0
, CCM_CCGR0_DSPI1_CTRL_MASK
);
351 clrsetbits_le32(&ccm
->ccgr1
, CCM_REG_CTRL_MASK
,
352 CCM_CCGR1_PIT_CTRL_MASK
| CCM_CCGR1_WDOGA5_CTRL_MASK
);
353 clrsetbits_le32(&ccm
->ccgr2
, CCM_REG_CTRL_MASK
,
354 CCM_CCGR2_IOMUXC_CTRL_MASK
| CCM_CCGR2_PORTA_CTRL_MASK
|
355 CCM_CCGR2_PORTB_CTRL_MASK
| CCM_CCGR2_PORTC_CTRL_MASK
|
356 CCM_CCGR2_PORTD_CTRL_MASK
| CCM_CCGR2_PORTE_CTRL_MASK
);
357 clrsetbits_le32(&ccm
->ccgr3
, CCM_REG_CTRL_MASK
,
358 CCM_CCGR3_ANADIG_CTRL_MASK
| CCM_CCGR3_SCSC_CTRL_MASK
);
359 clrsetbits_le32(&ccm
->ccgr4
, CCM_REG_CTRL_MASK
,
360 CCM_CCGR4_WKUP_CTRL_MASK
| CCM_CCGR4_CCM_CTRL_MASK
|
361 CCM_CCGR4_GPC_CTRL_MASK
| CCM_CCGR4_I2C0_CTRL_MASK
);
362 clrsetbits_le32(&ccm
->ccgr6
, CCM_REG_CTRL_MASK
,
363 CCM_CCGR6_OCOTP_CTRL_MASK
| CCM_CCGR6_DDRMC_CTRL_MASK
);
364 clrsetbits_le32(&ccm
->ccgr7
, CCM_REG_CTRL_MASK
,
365 CCM_CCGR7_SDHC1_CTRL_MASK
);
366 clrsetbits_le32(&ccm
->ccgr9
, CCM_REG_CTRL_MASK
,
367 CCM_CCGR9_FEC0_CTRL_MASK
| CCM_CCGR9_FEC1_CTRL_MASK
);
368 clrsetbits_le32(&ccm
->ccgr10
, CCM_REG_CTRL_MASK
,
369 CCM_CCGR10_NFC_CTRL_MASK
);
371 #ifdef CONFIG_USB_EHCI_VF
372 setbits_le32(&ccm
->ccgr1
, CCM_CCGR1_USBC0_CTRL_MASK
);
373 setbits_le32(&ccm
->ccgr7
, CCM_CCGR7_USBC1_CTRL_MASK
);
375 clrsetbits_le32(&anadig
->pll3_ctrl
, ANADIG_PLL3_CTRL_BYPASS
|
376 ANADIG_PLL3_CTRL_POWERDOWN
|
377 ANADIG_PLL3_CTRL_DIV_SELECT
,
378 ANADIG_PLL3_CTRL_ENABLE
);
379 clrsetbits_le32(&anadig
->pll7_ctrl
, ANADIG_PLL7_CTRL_BYPASS
|
380 ANADIG_PLL7_CTRL_POWERDOWN
|
381 ANADIG_PLL7_CTRL_DIV_SELECT
,
382 ANADIG_PLL7_CTRL_ENABLE
);
385 clrsetbits_le32(&anadig
->pll5_ctrl
, ANADIG_PLL5_CTRL_BYPASS
|
386 ANADIG_PLL5_CTRL_POWERDOWN
, ANADIG_PLL5_CTRL_ENABLE
|
387 ANADIG_PLL5_CTRL_DIV_SELECT
);
389 if (is_colibri_vf61()) {
390 clrsetbits_le32(&anadig
->pll2_ctrl
, ANADIG_PLL5_CTRL_BYPASS
|
391 ANADIG_PLL2_CTRL_POWERDOWN
,
392 ANADIG_PLL2_CTRL_ENABLE
|
393 ANADIG_PLL2_CTRL_DIV_SELECT
);
396 clrsetbits_le32(&anadig
->pll1_ctrl
, ANADIG_PLL1_CTRL_POWERDOWN
,
397 ANADIG_PLL1_CTRL_ENABLE
| ANADIG_PLL1_CTRL_DIV_SELECT
);
399 clrsetbits_le32(&ccm
->ccr
, CCM_CCR_OSCNT_MASK
,
400 CCM_CCR_FIRC_EN
| CCM_CCR_OSCNT(5));
402 /* See "Typical PLL Configuration" */
403 if (is_colibri_vf61()) {
404 pfd_clk_sel
= CCM_CCSR_PLL1_PFD_CLK_SEL(1);
405 ddr_clk_sel
= CCM_CCSR_DDRC_CLK_SEL(0);
407 pfd_clk_sel
= CCM_CCSR_PLL1_PFD_CLK_SEL(3);
408 ddr_clk_sel
= CCM_CCSR_DDRC_CLK_SEL(1);
411 clrsetbits_le32(&ccm
->ccsr
, CCM_REG_CTRL_MASK
, pfd_clk_sel
|
412 CCM_CCSR_PLL2_PFD4_EN
| CCM_CCSR_PLL2_PFD3_EN
|
413 CCM_CCSR_PLL2_PFD2_EN
| CCM_CCSR_PLL2_PFD1_EN
|
414 CCM_CCSR_PLL1_PFD4_EN
| CCM_CCSR_PLL1_PFD3_EN
|
415 CCM_CCSR_PLL1_PFD2_EN
| CCM_CCSR_PLL1_PFD1_EN
|
416 ddr_clk_sel
| CCM_CCSR_FAST_CLK_SEL(1) |
417 CCM_CCSR_SYS_CLK_SEL(4));
419 clrsetbits_le32(&ccm
->cacrr
, CCM_REG_CTRL_MASK
,
420 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
421 CCM_CACRR_ARM_CLK_DIV(0));
422 clrsetbits_le32(&ccm
->cscmr1
, CCM_REG_CTRL_MASK
,
423 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
424 CCM_CSCMR1_NFC_CLK_SEL(0));
425 clrsetbits_le32(&ccm
->cscdr1
, CCM_REG_CTRL_MASK
,
426 CCM_CSCDR1_RMII_CLK_EN
);
427 clrsetbits_le32(&ccm
->cscdr2
, CCM_REG_CTRL_MASK
,
428 CCM_CSCDR2_ESDHC1_EN
| CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
430 clrsetbits_le32(&ccm
->cscdr3
, CCM_REG_CTRL_MASK
,
431 CCM_CSCDR3_NFC_PRE_DIV(3));
432 clrsetbits_le32(&ccm
->cscmr2
, CCM_REG_CTRL_MASK
,
433 CCM_CSCMR2_RMII_CLK_SEL(2));
436 static void mscm_init(void)
438 struct mscm_ir
*mscmir
= (struct mscm_ir
*)MSCM_IR_BASE_ADDR
;
441 for (i
= 0; i
< MSCM_IRSPRC_NUM
; i
++)
442 writew(MSCM_IRSPRC_CP0_EN
, &mscmir
->irsprc
[i
]);
445 int board_phy_config(struct phy_device
*phydev
)
447 if (phydev
->drv
->config
)
448 phydev
->drv
->config(phydev
);
453 int board_early_init_f(void)
461 #ifdef CONFIG_NAND_VF610_NFC
465 #ifdef CONFIG_VYBRID_GPIO
469 #ifdef CONFIG_FSL_DSPI
476 #ifdef CONFIG_BOARD_LATE_INIT
477 int board_late_init(void)
479 struct src
*src
= (struct src
*)SRC_BASE_ADDR
;
481 /* Default memory arguments */
482 if (!getenv("memargs")) {
483 switch (gd
->ram_size
) {
486 setenv("memargs", "mem=128M");
490 setenv("memargs", "mem=256M");
493 printf("Failed detecting RAM size.\n");
497 if (((src
->sbmr2
& SRC_SBMR2_BMOD_MASK
) >> SRC_SBMR2_BMOD_SHIFT
)
498 == SRC_SBMR2_BMOD_SERIAL
) {
499 printf("Serial Downloader recovery mode, disable autoboot\n");
500 setenv("bootdelay", "-1");
505 #endif /* CONFIG_BOARD_LATE_INIT */
509 struct scsc_reg
*scsc
= (struct scsc_reg
*)SCSC_BASE_ADDR
;
511 /* address of boot parameters */
512 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
515 * Enable external 32K Oscillator
517 * The internal clock experiences significant drift
518 * so we must use the external oscillator in order
519 * to maintain correct time in the hwclock
522 setbits_le32(&scsc
->sosc_ctr
, SCSC_SOSC_CTR_SOSC_EN
);
524 #ifdef CONFIG_USB_EHCI_VF
525 gpio_request(USB_CDET_GPIO
, "usb-cdet-gpio");
533 if (is_colibri_vf61())
534 puts("Board: Colibri VF61\n");
536 puts("Board: Colibri VF50\n");
541 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
542 int ft_board_setup(void *blob
, bd_t
*bd
)
544 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
545 static struct node_info nodes
[] = {
546 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND
, }, /* NAND flash */
549 /* Update partition nodes using info from mtdparts env var */
550 puts(" Updating MTD partitions...\n");
551 fdt_fixup_mtdparts(blob
, nodes
, ARRAY_SIZE(nodes
));
554 return ft_common_board_setup(blob
, bd
);
558 #ifdef CONFIG_USB_EHCI_VF
559 int board_ehci_hcd_init(int port
)
561 imx_iomux_v3_setup_multiple_pads(usb_pads
, ARRAY_SIZE(usb_pads
));
565 /* USBC does not have PEN, also configured as USB client only */
568 gpio_request(USB_PEN_GPIO
, "usb-pen-gpio");
569 gpio_direction_output(USB_PEN_GPIO
, 0);
575 int board_usb_phy_mode(int port
)
580 * Port 0 is used only in client mode on Colibri Vybrid modules
581 * Check for state of USB client gpio pin and accordingly return
582 * USB_INIT_DEVICE or USB_INIT_HOST.
584 if (gpio_get_value(USB_CDET_GPIO
))
585 return USB_INIT_DEVICE
;
587 return USB_INIT_HOST
;
589 /* Port 1 is used only in host mode on Colibri Vybrid modules */
590 return USB_INIT_HOST
;
593 * There are only two USB controllers on Vybrid. Ideally we will
594 * not reach here. However return USB_INIT_HOST if we do.
596 return USB_INIT_HOST
;