board/total5200/total5200.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30 #include <netdev.h>
  31
  32 #include "sdram.h"
  33
  34 #if CONFIG_TOTAL5200_REV==2
  35 #include "mt48lc32m16a2-75.h"
  36 #else
  37 #include "mt48lc16m16a2-75.h"
  38 #endif
  39
  40 phys_size_t initdram (int board_type)
  41 {
  42         sdram_conf_t sdram_conf;
  43
  44         sdram_conf.ddr = SDRAM_DDR;
  45         sdram_conf.mode = SDRAM_MODE;
  46         sdram_conf.emode = 0;
  47         sdram_conf.control = SDRAM_CONTROL;
  48         sdram_conf.config1 = SDRAM_CONFIG1;
  49         sdram_conf.config2 = SDRAM_CONFIG2;
  50         sdram_conf.tapdelay = 0;
  51         return mpc5xxx_sdram_init (&sdram_conf);
  52 }
  53
  54 int checkboard (void)
  55 {
  56 #if CONFIG_TOTAL5200_REV==2
  57         puts ("Board: Total5200 Rev.2 ");
  58 #else
  59         puts ("Board: Total5200 ");
  60 #endif
  61
  62         /*
  63          * Retrieve FPGA Revision.
  64          */
  65         printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400));
  66
  67         /*
  68          * Take all peripherals in power-up mode.
  69          */
  70 #if CONFIG_TOTAL5200_REV==2
  71         *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70;
  72 #else
  73         *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70;
  74 #endif
  75
  76         return 0;
  77 }
  78
  79 #ifdef  CONFIG_PCI
  80 static struct pci_controller hose;
  81
  82 extern void pci_mpc5xxx_init(struct pci_controller *);
  83
  84 void pci_init_board(void)
  85 {
  86         pci_mpc5xxx_init(&hose);
  87 }
  88 #endif
  89
  90 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
  91
  92 /* IRDA_1 aka PSC6_3 (pin C13) */
  93 #define GPIO_IRDA_1     0x20000000UL
  94
  95 void init_ide_reset (void)
  96 {
  97         debug ("init_ide_reset\n");
  98
  99         /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
 100         *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
 101         *(vu_long *) MPC5XXX_GPIO_DIR    |= GPIO_IRDA_1;
 102 }
 103
 104 void ide_set_reset (int idereset)
 105 {
 106         debug ("ide_reset(%d)\n", idereset);
 107
 108         if (idereset) {
 109                 *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
 110         } else {
 111                 *(vu_long *) MPC5XXX_GPIO_DATA_O |=  GPIO_IRDA_1;
 112         }
 113 }
 114 #endif
 115
 116 #ifdef CONFIG_VIDEO_SED13806
 117 #include <sed13806.h>
 118
 119 #define DISPLAY_WIDTH   640
 120 #define DISPLAY_HEIGHT  480
 121
 122 #ifdef CONFIG_VIDEO_SED13806_8BPP
 123 #error CONFIG_VIDEO_SED13806_8BPP not supported.
 124 #endif /* CONFIG_VIDEO_SED13806_8BPP */
 125
 126 #ifdef CONFIG_VIDEO_SED13806_16BPP
 127 static const S1D_REGS init_regs [] =
 128 {
 129     {0x0001,0x00},   /* Miscellaneous Register */
 130     {0x01FC,0x00},   /* Display Mode Register */
 131     {0x0004,0x00},   /* General IO Pins Configuration Register 0 */
 132     {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
 133     {0x0008,0x00},   /* General IO Pins Control Register 0 */
 134     {0x0009,0x00},   /* General IO Pins Control Register 1 */
 135     {0x0010,0x02},   /* Memory Clock Configuration Register */
 136     {0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
 137     {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
 138     {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
 139     {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
 140     {0x0021,0x03},   /* DRAM Refresh Rate Register */
 141     {0x002A,0x00},   /* DRAM Timings Control Register 0 */
 142     {0x002B,0x01},   /* DRAM Timings Control Register 1 */
 143     {0x0020,0x80},   /* Memory Configuration Register */
 144     {0x0030,0x25},   /* Panel Type Register */
 145     {0x0031,0x00},   /* MOD Rate Register */
 146     {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
 147     {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
 148     {0x0035,0x01},   /* TFT FPLINE Start Position Register */
 149     {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
 150     {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
 151     {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
 152     {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
 153     {0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
 154     {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
 155     {0x0040,0x05},   /* LCD Display Mode Register */
 156     {0x0041,0x00},   /* LCD Miscellaneous Register */
 157     {0x0042,0x00},   /* LCD Display Start Address Register 0 */
 158     {0x0043,0x00},   /* LCD Display Start Address Register 1 */
 159     {0x0044,0x00},   /* LCD Display Start Address Register 2 */
 160     {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
 161     {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
 162     {0x0048,0x00},   /* LCD Pixel Panning Register */
 163     {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
 164     {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
 165     {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
 166     {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
 167     {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
 168     {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
 169     {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
 170     {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
 171     {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
 172     {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
 173     {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
 174     {0x005B,0x10},   /* TV Output Control Register */
 175     {0x0060,0x05},   /* CRT/TV Display Mode Register */
 176     {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
 177     {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
 178     {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
 179     {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
 180     {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
 181     {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
 182     {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
 183     {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
 184     {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
 185     {0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
 186     {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
 187     {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
 188     {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
 189     {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
 190     {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
 191     {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
 192     {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
 193     {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
 194     {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
 195     {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
 196     {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
 197     {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
 198     {0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
 199     {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
 200     {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
 201     {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
 202     {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
 203     {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
 204     {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
 205     {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
 206     {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
 207     {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
 208     {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
 209     {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
 210     {0x0100,0x00},   /* BitBlt Control Register 0 */
 211     {0x0101,0x00},   /* BitBlt Control Register 1 */
 212     {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
 213     {0x0103,0x00},   /* BitBlt Operation Register */
 214     {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
 215     {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
 216     {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
 217     {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
 218     {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
 219     {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
 220     {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
 221     {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
 222     {0x0110,0x00},   /* BitBlt Width Register 0 */
 223     {0x0111,0x00},   /* BitBlt Width Register 1 */
 224     {0x0112,0x00},   /* BitBlt Height Register 0 */
 225     {0x0113,0x00},   /* BitBlt Height Register 1 */
 226     {0x0114,0x00},   /* BitBlt Background Color Register 0 */
 227     {0x0115,0x00},   /* BitBlt Background Color Register 1 */
 228     {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
 229     {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
 230     {0x01E0,0x00},   /* Look-Up Table Mode Register */
 231     {0x01E2,0x00},   /* Look-Up Table Address Register */
 232     {0x01E4,0x00},   /* Look-Up Table Data Register */
 233     {0x01F0,0x00},   /* Power Save Configuration Register */
 234     {0x01F1,0x00},   /* Power Save Status Register */
 235     {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
 236     {0x01FC,0x01},   /* Display Mode Register */
 237     {0, 0}
 238 };
 239 #endif /* CONFIG_VIDEO_SED13806_16BPP */
 240
 241 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 242 /* Return text to be printed besides the logo. */
 243 void video_get_info_str (int line_number, char *info)
 244 {
 245         if (line_number == 1) {
 246 #if CONFIG_TOTAL5200_REV==1
 247                 strcpy (info, " Total5200");
 248 #elif CONFIG_TOTAL5200_REV==2
 249                 strcpy (info, " Total5200 Rev.2");
 250 #else
 251 #error CONFIG_TOTAL5200_REV must be 1 or 2.
 252 #endif
 253         } else {
 254                 info [0] = '\0';
 255         }
 256 }
 257 #endif
 258
 259 /* Returns  SED13806 base address. First thing called in the driver. */
 260 unsigned int board_video_init (void)
 261 {
 262         return CONFIG_SYS_LCD_BASE;
 263 }
 264
 265 /* Called after initializing the SED13806 and before clearing the screen. */
 266 void board_validate_screen (unsigned int base)
 267 {
 268 }
 269
 270 /* Return a pointer to the initialization sequence. */
 271 const S1D_REGS *board_get_regs (void)
 272 {
 273         return init_regs;
 274 }
 275
 276 int board_get_width (void)
 277 {
 278         return DISPLAY_WIDTH;
 279 }
 280
 281 int board_get_height (void)
 282 {
 283         return DISPLAY_HEIGHT;
 284 }
 285
 286 #endif /* CONFIG_VIDEO_SED13806 */
 287
 288 int board_eth_init(bd_t *bis)
 289 {
 290         cpu_eth_init(bis); /* Built in FEC comes first */
 291         return pci_eth_init(bis);
 292 }