3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/mpc8349_pci.h>
17 #include <mtd/cfi_flash.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 #define IOSYNC asm("eieio")
22 #define ISYNC asm("isync")
23 #define SYNC asm("sync")
24 #define FPW FLASH_PORT_WIDTH
25 #define FPWV FLASH_PORT_WIDTHV
27 #define DDR_MAX_SIZE_PER_CS 0x20000000
29 #if defined(DDR_CASLAT_20)
30 #define TIMING_CASLAT TIMING_CFG1_CASLAT_20
31 #define MODE_CASLAT DDR_MODE_CASLAT_20
33 #define TIMING_CASLAT TIMING_CFG1_CASLAT_25
34 #define MODE_CASLAT DDR_MODE_CASLAT_25
37 #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
40 /* External definitions */
41 ulong
flash_get_size (ulong base
, int banknum
);
44 static int detect_num_flash_banks(void);
45 static long int get_ddr_bank_size(short cs
, long *base
);
46 static void set_cs_bounds(short cs
, ulong base
, ulong size
);
47 static void set_cs_config(short cs
, long config
);
48 static void set_ddr_config(void);
51 static volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
53 /**************************************************************************
54 * Board initialzation after relocation to RAM. Used to detect the number
55 * of Flash banks on TQM834x.
57 int board_early_init_r (void) {
58 /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
59 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
)im
)
62 /* detect the number of Flash banks */
63 return detect_num_flash_banks();
66 /**************************************************************************
67 * DRAM initalization and size detection
75 /* during size detection, set up the max DDRLAW size */
76 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_BASE
;
77 im
->sysconf
.ddrlaw
[0].ar
= (LAWAR_EN
| LAWAR_SIZE_2G
);
79 /* set CS bounds to maximum size */
80 for(cs
= 0; cs
< 4; ++cs
) {
82 CONFIG_SYS_DDR_BASE
+ (cs
* DDR_MAX_SIZE_PER_CS
),
85 set_cs_config(cs
, INITIAL_CS_CONFIG
);
88 /* configure ddr controller */
93 /* enable DDR controller */
94 im
->ddr
.sdram_cfg
= (SDRAM_CFG_MEM_EN
|
96 SDRAM_CFG_SDRAM_TYPE_DDR1
);
102 for(cs
= 0; cs
< 4; ++cs
) {
103 debug("\nDetecting Bank%d\n", cs
);
105 bank_size
= get_ddr_bank_size(cs
,
106 (long *)(CONFIG_SYS_DDR_BASE
+ size
));
109 debug("DDR Bank%d size: %ld MiB\n\n", cs
, bank_size
>> 20);
111 /* exit if less than one bank */
112 if(size
< DDR_MAX_SIZE_PER_CS
) break;
120 /**************************************************************************
123 int checkboard (void)
125 puts("Board: TQM834x\n");
128 volatile immap_t
* immr
;
131 immr
= (immap_t
*)CONFIG_SYS_IMMR
;
132 if (!(immr
->reset
.rcwh
& HRCWH_PCI_HOST
)) {
133 printf("PCI: NOT in host mode..?!\n");
139 if (immr
->reset
.rcwh
& HRCWH_64_BIT_PCI
)
145 printf("PCI1: %d bit, %d MHz\n", w
, f
/ 1000000);
147 printf("PCI: disabled\n");
153 /**************************************************************************
157 *************************************************************************/
159 /**************************************************************************
160 * Detect the number of flash banks (1 or 2). Store it in
161 * a global variable tqm834x_num_flash_banks.
162 * Bank detection code based on the Monitor code.
164 static int detect_num_flash_banks(void)
166 typedef unsigned long FLASH_PORT_WIDTH
;
167 typedef volatile unsigned long FLASH_PORT_WIDTHV
;
176 cfi_flash_num_flash_banks
= 2; /* assume two banks */
178 /* Get bank 1 and 2 information */
179 bank1_size
= flash_get_size(CONFIG_SYS_FLASH_BASE
, 0);
180 debug("Bank1 size: %lu\n", bank1_size
);
181 bank2_size
= flash_get_size(CONFIG_SYS_FLASH_BASE
+ bank1_size
, 1);
182 debug("Bank2 size: %lu\n", bank2_size
);
183 total_size
= bank1_size
+ bank2_size
;
185 if (bank2_size
> 0) {
186 /* Seems like we've got bank 2, but maybe it's mirrored 1 */
188 /* Set the base addresses */
189 bank1_base
= (FPWV
*) (CONFIG_SYS_FLASH_BASE
);
190 bank2_base
= (FPWV
*) (CONFIG_SYS_FLASH_BASE
+ bank1_size
);
192 /* Put bank 2 into CFI command mode and read */
193 bank2_base
[0x55] = 0x00980098;
196 bank2_read
= bank2_base
[0x10];
198 /* Read from bank 1 (it's in read mode) */
199 bank1_read
= bank1_base
[0x10];
202 bank1_base
[0] = 0x00F000F0;
203 bank2_base
[0] = 0x00F000F0;
205 if (bank2_read
== bank1_read
) {
207 * Looks like just one bank, but not sure yet. Let's
208 * read from bank 2 in autosoelect mode.
210 bank2_base
[0x0555] = 0x00AA00AA;
211 bank2_base
[0x02AA] = 0x00550055;
212 bank2_base
[0x0555] = 0x00900090;
215 bank2_read
= bank2_base
[0x10];
217 /* Read from bank 1 (it's in read mode) */
218 bank1_read
= bank1_base
[0x10];
221 bank1_base
[0] = 0x00F000F0;
222 bank2_base
[0] = 0x00F000F0;
224 if (bank2_read
== bank1_read
) {
226 * In both CFI command and autoselect modes,
227 * we got the some data reading from Flash.
228 * There is only one mirrored bank.
230 cfi_flash_num_flash_banks
= 1;
231 total_size
= bank1_size
;
236 debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks
);
238 /* set OR0 and BR0 */
239 set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH
|
240 (-(total_size
) & OR_GPCM_AM
));
241 set_lbc_br(0, (CONFIG_SYS_FLASH_BASE
& BR_BA
) |
242 (BR_MS_GPCM
| BR_PS_32
| BR_V
));
247 /*************************************************************************
248 * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
250 static long int get_ddr_bank_size(short cs
, long *base
)
252 /* This array lists all valid DDR SDRAM configurations, with
253 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
254 * The last entry has to to have size equal 0 and is igonred during
255 * autodection. Bank sizes must be in increasing order of size
262 {CSCONFIG_ROW_BIT_12
, CSCONFIG_COL_BIT_8
, 32 << 20},
263 {CSCONFIG_ROW_BIT_12
, CSCONFIG_COL_BIT_9
, 64 << 20},
264 {CSCONFIG_ROW_BIT_12
, CSCONFIG_COL_BIT_10
, 128 << 20},
265 {CSCONFIG_ROW_BIT_13
, CSCONFIG_COL_BIT_9
, 128 << 20},
266 {CSCONFIG_ROW_BIT_13
, CSCONFIG_COL_BIT_10
, 256 << 20},
267 {CSCONFIG_ROW_BIT_13
, CSCONFIG_COL_BIT_11
, 512 << 20},
268 {CSCONFIG_ROW_BIT_14
, CSCONFIG_COL_BIT_10
, 512 << 20},
269 {CSCONFIG_ROW_BIT_14
, CSCONFIG_COL_BIT_11
, 1024 << 20},
278 for(i
= 0; conf
[i
].size
!= 0; ++i
) {
280 /* set sdram bank configuration */
281 set_cs_config(cs
, CSCONFIG_EN
| conf
[i
].col
| conf
[i
].row
);
283 debug("Getting RAM size...\n");
284 size
= get_ram_size(base
, DDR_MAX_SIZE_PER_CS
);
286 if((size
== conf
[i
].size
) && (i
== detected
+ 1))
289 debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
298 /* disable empty cs */
299 debug("\nNo valid configurations for CS%d, disabling...\n", cs
);
300 set_cs_config(cs
, 0);
304 debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
305 conf
[detected
].row
, conf
[detected
].col
, conf
[detected
].size
>> 20, base
);
307 /* configure cs ro detected params */
308 set_cs_config(cs
, CSCONFIG_EN
| conf
[detected
].row
|
311 set_cs_bounds(cs
, (long)base
, conf
[detected
].size
);
313 return(conf
[detected
].size
);
316 /**************************************************************************
317 * Sets DDR bank CS bounds.
319 static void set_cs_bounds(short cs
, ulong base
, ulong size
)
321 debug("Setting bounds %08lx, %08lx for cs %d\n", base
, size
, cs
);
323 im
->ddr
.csbnds
[cs
].csbnds
= 0x00000000;
325 im
->ddr
.csbnds
[cs
].csbnds
=
326 ((base
>> CSBNDS_SA_SHIFT
) & CSBNDS_SA
) |
327 (((base
+ size
- 1) >> CSBNDS_EA_SHIFT
) &
333 /**************************************************************************
334 * Sets DDR banks CS configuration.
335 * config == 0x00000000 disables the CS.
337 static void set_cs_config(short cs
, long config
)
339 debug("Setting config %08lx for cs %d\n", config
, cs
);
340 im
->ddr
.cs_config
[cs
] = config
;
344 /**************************************************************************
345 * Sets DDR clocks, timings and configuration.
347 static void set_ddr_config(void) {
349 im
->ddr
.sdram_clk_cntl
= DDR_SDRAM_CLK_CNTL_SS_EN
|
350 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
;
353 /* timing configuration */
354 im
->ddr
.timing_cfg_1
=
355 (4 << TIMING_CFG1_PRETOACT_SHIFT
) |
356 (7 << TIMING_CFG1_ACTTOPRE_SHIFT
) |
357 (4 << TIMING_CFG1_ACTTORW_SHIFT
) |
358 (5 << TIMING_CFG1_REFREC_SHIFT
) |
359 (3 << TIMING_CFG1_WRREC_SHIFT
) |
360 (3 << TIMING_CFG1_ACTTOACT_SHIFT
) |
361 (1 << TIMING_CFG1_WRTORD_SHIFT
) |
362 (TIMING_CFG1_CASLAT
& TIMING_CASLAT
);
364 im
->ddr
.timing_cfg_2
=
365 TIMING_CFG2_CPO_DEF
|
366 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT
);
369 /* don't enable DDR controller yet */
372 SDRAM_CFG_SDRAM_TYPE_DDR1
;
377 ((DDR_MODE_EXT_MODEREG
| DDR_MODE_WEAK
) <<
378 SDRAM_MODE_ESD_SHIFT
) |
379 ((DDR_MODE_MODEREG
| DDR_MODE_BLEN_4
) <<
380 SDRAM_MODE_SD_SHIFT
) |
381 ((DDR_MODE_CASLAT
<< SDRAM_MODE_SD_SHIFT
) &
385 /* Set fast SDRAM refresh rate */
386 im
->ddr
.sdram_interval
=
387 (DDR_REFINT_166MHZ_7US
<< SDRAM_INTERVAL_REFINT_SHIFT
) |
388 (DDR_BSTOPRE
<< SDRAM_INTERVAL_BSTOPRE_SHIFT
);
391 /* Workaround for DDR6 Erratum
392 * see MPC8349E Device Errata Rev.8, 2/2006
393 * This workaround influences the MPC internal "input enables"
394 * dependent on CAS latency and MPC revision. According to errata
395 * sheet the internal reserved registers for this workaround are
396 * not available from revision 2.0 and up.
399 /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
402 if ((im
->sysconf
.spridr
& SPRIDR_REVID
) < 0x200) {
404 /* There is a internal reserved register at IMMRBAR+0x2F00
405 * which has to be written with a certain value defined by
408 u32
*reserved_p
= (u32
*)((u8
*)im
+ 0x2f00);
410 #if defined(DDR_CASLAT_20)
411 *reserved_p
= 0x201c0000;
413 *reserved_p
= 0x202c0000;
418 #ifdef CONFIG_OF_BOARD_SETUP
419 int ft_board_setup(void *blob
, bd_t
*bd
)
421 ft_cpu_setup(blob
, bd
);
424 ft_pci_setup(blob
, bd
);
425 #endif /* CONFIG_PCI */
429 #endif /* CONFIG_OF_BOARD_SETUP */