board/tqc/tqma6/tqma6_mba6.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   4  *
   5  * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
   6  * Author: Markus Niebel <markus.niebel@tq-group.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <linux/errno.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20
  21 #include <common.h>
  22 #include <fsl_esdhc.h>
  23 #include <libfdt.h>
  24 #include <malloc.h>
  25 #include <i2c.h>
  26 #include <micrel.h>
  27 #include <miiphy.h>
  28 #include <mmc.h>
  29 #include <netdev.h>
  30
  31 #include "tqma6_bb.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  36         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
  39         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
  42         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  45         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  46
  47 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  48         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  49
  50 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  51         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  52
  53 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  54         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |                       \
  55         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  56
  57 #if defined(CONFIG_TQMA6Q)
  58
  59 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0790
  60 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e07ac
  61
  62 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
  63
  64 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0768
  65 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e0788
  66
  67 #else
  68
  69 #error "need to select module"
  70
  71 #endif
  72
  73 #define ENET_RX_PAD_CTRL        (PAD_CTL_DSE_34ohm)
  74 #define ENET_TX_PAD_CTRL        (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
  75 #define ENET_CLK_PAD_CTRL       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  76                                  PAD_CTL_DSE_34ohm)
  77 #define ENET_MDIO_PAD_CTRL      (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  78                                  PAD_CTL_DSE_60ohm)
  79
  80 /* disable on die termination for RGMII */
  81 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE        0x00000000
  82 /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
  83 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V       0x00080000
  84 /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
  85 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V       0x000C0000
  86
  87 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
  88
  89 static iomux_v3_cfg_t const mba6_enet_pads[] = {
  90         NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO,      ENET_MDIO_PAD_CTRL),
  91         NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC,        ENET_MDIO_PAD_CTRL),
  92
  93         NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC,      ENET_TX_PAD_CTRL),
  94         NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0,      ENET_TX_PAD_CTRL),
  95         NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1,      ENET_TX_PAD_CTRL),
  96         NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2,      ENET_TX_PAD_CTRL),
  97         NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3,      ENET_TX_PAD_CTRL),
  98         NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
  99                      ENET_TX_PAD_CTRL),
 100         NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
 101         /*
 102          * these pins are also used for config strapping by phy
 103          */
 104         NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0,      ENET_RX_PAD_CTRL),
 105         NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1,      ENET_RX_PAD_CTRL),
 106         NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2,      ENET_RX_PAD_CTRL),
 107         NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3,      ENET_RX_PAD_CTRL),
 108         NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC,      ENET_RX_PAD_CTRL),
 109         NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
 110                      ENET_RX_PAD_CTRL),
 111         /* KSZ9031 PHY Reset */
 112         NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25,   GPIO_OUT_PAD_CTRL),
 113 };
 114
 115 static void mba6_setup_iomuxc_enet(void)
 116 {
 117         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 118
 119         /* clear gpr1[ENET_CLK_SEL] for externel clock */
 120         clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 121
 122         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
 123                      (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
 124         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
 125                      (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
 126
 127         imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
 128                                          ARRAY_SIZE(mba6_enet_pads));
 129
 130         /* Reset PHY */
 131         gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
 132         /* Need delay 10ms after power on according to KSZ9031 spec */
 133         mdelay(10);
 134         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 135         /*
 136          * KSZ9031 manual: 100 usec wait time after reset before communication
 137          * over MDIO
 138          * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
 139          * reset before the phy sees a high level
 140          */
 141         mdelay(15);
 142 }
 143
 144 static iomux_v3_cfg_t const mba6_uart2_pads[] = {
 145         NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
 146         NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
 147 };
 148
 149 static void mba6_setup_iomuxc_uart(void)
 150 {
 151         imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
 152                                          ARRAY_SIZE(mba6_uart2_pads));
 153 }
 154
 155 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 156 #define USDHC2_WP_GPIO  IMX_GPIO_NR(1, 2)
 157
 158 int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
 159 {
 160         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 161         int ret = 0;
 162
 163         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
 164                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 165
 166         return ret;
 167 }
 168
 169 int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
 170 {
 171         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 172         int ret = 0;
 173
 174         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
 175                 ret = gpio_get_value(USDHC2_WP_GPIO);
 176
 177         return ret;
 178 }
 179
 180 static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
 181         .esdhc_base = USDHC2_BASE_ADDR,
 182         .max_bus_width = 4,
 183 };
 184
 185 static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
 186         NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK,          USDHC_CLK_PAD_CTRL),
 187         NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD,          USDHC_PAD_CTRL),
 188         NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0,       USDHC_PAD_CTRL),
 189         NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1,       USDHC_PAD_CTRL),
 190         NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2,       USDHC_PAD_CTRL),
 191         NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3,       USDHC_PAD_CTRL),
 192         /* CD */
 193         NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04,        GPIO_IN_PAD_CTRL),
 194         /* WP */
 195         NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02,        GPIO_IN_PAD_CTRL),
 196 };
 197
 198 int tqma6_bb_board_mmc_init(bd_t *bis)
 199 {
 200         imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
 201                                          ARRAY_SIZE(mba6_usdhc2_pads));
 202         gpio_direction_input(USDHC2_CD_GPIO);
 203         gpio_direction_input(USDHC2_WP_GPIO);
 204
 205         mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 206         if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
 207                 puts("Warning: failed to initialize SD\n");
 208
 209         return 0;
 210 }
 211
 212 static struct i2c_pads_info mba6_i2c1_pads = {
 213 /* I2C1: MBa6x */
 214         .scl = {
 215                 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
 216                                          I2C_PAD_CTRL),
 217                 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
 218                                           I2C_PAD_CTRL),
 219                 .gp = IMX_GPIO_NR(5, 27)
 220         },
 221         .sda = {
 222                 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
 223                                          I2C_PAD_CTRL),
 224                 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
 225                                           I2C_PAD_CTRL),
 226                 .gp = IMX_GPIO_NR(5, 26)
 227         }
 228 };
 229
 230 static void mba6_setup_i2c(void)
 231 {
 232         int ret;
 233         /*
 234          * use logical index for bus, e.g. I2C1 -> 0
 235          * warn on error
 236          */
 237         ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
 238         if (ret)
 239                 printf("setup I2C1 failed: %d\n", ret);
 240 }
 241
 242 int board_phy_config(struct phy_device *phydev)
 243 {
 244 /*
 245  * optimized pad skew values depends on CPU variant on the TQMa6x module:
 246  * CONFIG_TQMA6Q: i.MX6Q/D
 247  * CONFIG_TQMA6S: i.MX6S
 248  * CONFIG_TQMA6DL: i.MX6DL
 249  */
 250 #if defined(CONFIG_TQMA6Q)
 251 #define MBA6X_KSZ9031_CTRL_SKEW 0x0032
 252 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
 253 #define MBA6X_KSZ9031_RX_SKEW   0x3333
 254 #define MBA6X_KSZ9031_TX_SKEW   0x2036
 255 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
 256 #define MBA6X_KSZ9031_CTRL_SKEW 0x0030
 257 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
 258 #define MBA6X_KSZ9031_RX_SKEW   0x3333
 259 #define MBA6X_KSZ9031_TX_SKEW   0x2052
 260 #else
 261 #error
 262 #endif
 263         /* min rx/tx ctrl delay */
 264         ksz9031_phy_extended_write(phydev, 2,
 265                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 266                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 267                                    MBA6X_KSZ9031_CTRL_SKEW);
 268         /* min rx delay */
 269         ksz9031_phy_extended_write(phydev, 2,
 270                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 271                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 272                                    MBA6X_KSZ9031_RX_SKEW);
 273         /* max tx delay */
 274         ksz9031_phy_extended_write(phydev, 2,
 275                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 276                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 277                                    MBA6X_KSZ9031_TX_SKEW);
 278         /* rx/tx clk skew */
 279         ksz9031_phy_extended_write(phydev, 2,
 280                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 281                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 282                                    MBA6X_KSZ9031_CLK_SKEW);
 283
 284         phydev->drv->config(phydev);
 285
 286         return 0;
 287 }
 288
 289 int board_eth_init(bd_t *bis)
 290 {
 291         uint32_t base = IMX_FEC_BASE;
 292         struct mii_dev *bus = NULL;
 293         struct phy_device *phydev = NULL;
 294         int ret;
 295
 296         bus = fec_get_miibus(base, -1);
 297         if (!bus)
 298                 return -EINVAL;
 299         /* scan phy */
 300         phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
 301                                         PHY_INTERFACE_MODE_RGMII);
 302
 303         if (!phydev) {
 304                 ret = -EINVAL;
 305                 goto free_bus;
 306         }
 307         ret  = fec_probe(bis, -1, base, bus, phydev);
 308         if (ret)
 309                 goto free_phydev;
 310
 311         return 0;
 312
 313 free_phydev:
 314         free(phydev);
 315 free_bus:
 316         free(bus);
 317         return ret;
 318 }
 319
 320 int tqma6_bb_board_early_init_f(void)
 321 {
 322         mba6_setup_iomuxc_uart();
 323
 324         return 0;
 325 }
 326
 327 int tqma6_bb_board_init(void)
 328 {
 329         mba6_setup_i2c();
 330         /* do it here - to have reset completed */
 331         mba6_setup_iomuxc_enet();
 332
 333         return 0;
 334 }
 335
 336 int tqma6_bb_board_late_init(void)
 337 {
 338         return 0;
 339 }
 340
 341 const char *tqma6_bb_get_boardname(void)
 342 {
 343         return "MBa6x";
 344 }
 345
 346 /*
 347  * Device Tree Support
 348  */
 349 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 350 void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
 351 {
 352  /* TBD */
 353 }
 354 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */