board/tqm85xx/sdram.c

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <common.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_85xx.h>
  28 #include <asm/processor.h>
  29 #include <asm/mmu.h>
  30
  31 struct sdram_conf_s {
  32         unsigned long size;
  33         unsigned long reg;
  34 };
  35
  36 typedef struct sdram_conf_s sdram_conf_t;
  37
  38 sdram_conf_t ddr_cs_conf[] = {
  39         {(512 << 20), 0x80000202},      /* 512MB, 14x10(4)      */
  40         {(256 << 20), 0x80000102},      /* 256MB, 13x10(4)      */
  41         {(128 << 20), 0x80000101},      /* 128MB, 13x9(4)       */
  42         {(64  << 20), 0x80000001},      /* 64MB,  12x9(4)       */
  43 };
  44
  45 #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
  46
  47 int cas_latency(void);
  48
  49 /*
  50  * Autodetect onboard DDR SDRAM on 85xx platforms
  51  *
  52  * NOTE: Some of the hardcoded values are hardware dependant,
  53  *       so this should be extended for other future boards
  54  *       using this routine!
  55  */
  56 long int sdram_setup(int casl)
  57 {
  58         int i;
  59         volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
  60         unsigned long cfg_ddr_timing1;
  61         unsigned long cfg_ddr_mode;
  62
  63         /*
  64          * Disable memory controller.
  65          */
  66         ddr->cs0_config = 0;
  67         ddr->sdram_cfg = 0;
  68
  69         switch (casl) {
  70         case 20:
  71                 cfg_ddr_timing1 = 0x47405331 | (3 << 16);
  72                 cfg_ddr_mode = 0x40020002 | (2 << 4);
  73                 break;
  74
  75         case 25:
  76                 cfg_ddr_timing1 = 0x47405331 | (4 << 16);
  77                 cfg_ddr_mode = 0x40020002 | (6 << 4);
  78                 break;
  79
  80         case 30:
  81         default:
  82                 cfg_ddr_timing1 = 0x47405331 | (5 << 16);
  83                 cfg_ddr_mode = 0x40020002 | (3 << 4);
  84                 break;
  85         }
  86
  87         ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
  88         ddr->cs0_config = ddr_cs_conf[0].reg;
  89         ddr->timing_cfg_1 = cfg_ddr_timing1;
  90         ddr->timing_cfg_2 = 0x00000800;         /* P9-45,may need tuning */
  91         ddr->sdram_mode = cfg_ddr_mode;
  92         ddr->sdram_interval = 0x05160100;       /* autocharge,no open page */
  93         ddr->err_disable = 0x0000000D;
  94
  95         asm ("sync;isync;msync");
  96         udelay(1000);
  97
  98         ddr->sdram_cfg = 0xc2000000;            /* unbuffered,no DYN_PWR */
  99         asm ("sync; isync; msync");
 100         udelay(1000);
 101
 102         for (i=0; i<N_DDR_CS_CONF; i++) {
 103                 ddr->cs0_config = ddr_cs_conf[i].reg;
 104
 105                 if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
 106                         /*
 107                          * OK, size detected -> all done
 108                          */
 109                         return ddr_cs_conf[i].size;
 110                 }
 111         }
 112
 113         return 0;                               /* nothing found !              */
 114 }
 115
 116 void board_add_ram_info(int use_default)
 117 {
 118         int casl;
 119
 120         if (use_default)
 121                 casl = CONFIG_DDR_DEFAULT_CL;
 122         else
 123                 casl = cas_latency();
 124
 125         puts(" (CL=");
 126         switch (casl) {
 127         case 20:
 128                 puts("2)");
 129                 break;
 130
 131         case 25:
 132                 puts("2.5)");
 133                 break;
 134
 135         case 30:
 136                 puts("3)");
 137                 break;
 138         }
 139 }
 140
 141 long int initdram (int board_type)
 142 {
 143         long dram_size = 0;
 144         int casl;
 145
 146 #if defined(CONFIG_DDR_DLL)
 147         /*
 148          * This DLL-Override only used on TQM8540 and TQM8560
 149          */
 150         {
 151                 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 152                 int i,x;
 153
 154                 x = 10;
 155
 156                 /*
 157                  * Work around to stabilize DDR DLL
 158                  */
 159                 gur->ddrdllcr = 0x81000000;
 160                 asm("sync;isync;msync");
 161                 udelay (200);
 162                 while (gur->ddrdllcr != 0x81000100) {
 163                         gur->devdisr = gur->devdisr | 0x00010000;
 164                         asm("sync;isync;msync");
 165                         for (i=0; i<x; i++)
 166                                 ;
 167                         gur->devdisr = gur->devdisr & 0xfff7ffff;
 168                         asm("sync;isync;msync");
 169                         x++;
 170                 }
 171         }
 172 #endif
 173
 174         casl = cas_latency();
 175         dram_size = sdram_setup(casl);
 176         if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
 177                 /*
 178                  * Try again with default CAS latency
 179                  */
 180                 puts("Problem with CAS lantency");
 181                 board_add_ram_info(1);
 182                 puts(", using default CL!\n");
 183                 casl = CONFIG_DDR_DEFAULT_CL;
 184                 dram_size = sdram_setup(casl);
 185                 puts("       ");
 186         }
 187
 188         return dram_size;
 189 }
 190
 191 #if defined(CFG_DRAM_TEST)
 192 int testdram (void)
 193 {
 194         uint *pstart = (uint *) CFG_MEMTEST_START;
 195         uint *pend = (uint *) CFG_MEMTEST_END;
 196         uint *p;
 197
 198         printf ("SDRAM test phase 1:\n");
 199         for (p = pstart; p < pend; p++)
 200                 *p = 0xaaaaaaaa;
 201
 202         for (p = pstart; p < pend; p++) {
 203                 if (*p != 0xaaaaaaaa) {
 204                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 205                         return 1;
 206                 }
 207         }
 208
 209         printf ("SDRAM test phase 2:\n");
 210         for (p = pstart; p < pend; p++)
 211                 *p = 0x55555555;
 212
 213         for (p = pstart; p < pend; p++) {
 214                 if (*p != 0x55555555) {
 215                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 216                         return 1;
 217                 }
 218         }
 219
 220         printf ("SDRAM test passed.\n");
 221         return 0;
 222 }
 223 #endif