board/tqm85xx/tqm85xx.c

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * Copyright 2004 Freescale Semiconductor.
   6  * (C) Copyright 2002,2003, Motorola Inc.
   7  * Xianghua Xiao, (X.Xiao@motorola.com)
   8  *
   9  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30
  31 #include <common.h>
  32 #include <pci.h>
  33 #include <asm/processor.h>
  34 #include <asm/immap_85xx.h>
  35 #include <ioports.h>
  36 #include <spd.h>
  37 #include <flash.h>
  38
  39 extern flash_info_t flash_info[];       /* FLASH chips info */
  40
  41 void local_bus_init (void);
  42 long int fixed_sdram (void);
  43 ulong flash_get_size (ulong base, int banknum);
  44
  45 #ifdef CONFIG_CPM2
  46 /*
  47  * I/O Port configuration table
  48  *
  49  * if conf is 1, then that port pin will be configured at boot time
  50  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  51  */
  52
  53 const iop_conf_t iop_conf_tab[4][32] = {
  54
  55     /* Port A configuration */
  56     {   /*            conf ppar psor pdir podr pdat */
  57         /* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
  58         /* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
  59         /* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
  60         /* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
  61         /* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
  62         /* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
  63         /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  64         /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  65         /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  66         /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  67         /* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
  68         /* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
  69         /* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
  70         /* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
  71         /* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
  72         /* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
  73         /* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
  74         /* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
  75         /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  76         /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  77         /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  78         /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  79         /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  80         /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  81         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  82         /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  83         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  84         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  85         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  86         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  87         /* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* FREERUN */
  88         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  89     },
  90
  91     /* Port B configuration */
  92     {   /*            conf ppar psor pdir podr pdat */
  93         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  94         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  95         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  96         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  97         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  98         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  99         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
 100         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
 101         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
 102         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
 103         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 104         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 105         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 106         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 107         /* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 108         /* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 109         /* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 110         /* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 111         /* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 112         /* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 113         /* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 114         /* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 115         /* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 116         /* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 117         /* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 118         /* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 119         /* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 120         /* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 121         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 122         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 123         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 124         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 125     },
 126
 127     /* Port C */
 128     {   /*            conf ppar psor pdir podr pdat */
 129         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 130         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 131         /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 132         /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 133         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 134         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 135         /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 136         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 137         /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 138         /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 139         /* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 140         /* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 141         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 142         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 143         /* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* PC17 */
 144         /* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 145         /* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
 146         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 147         /* PC13 */ {   0,   1,   0,   0,   0,   0   }, /* PC13 */
 148         /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 149         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 150         /* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
 151         /* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 152         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 153         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 154         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 155         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 156         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 157         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 158         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 159         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 160         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 161     },
 162
 163     /* Port D */
 164     {   /*            conf ppar psor pdir podr pdat */
 165         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 166         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 167         /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 168         /* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* PD28 */
 169         /* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* PD27 */
 170         /* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* PD26 */
 171         /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 172         /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 173         /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 174         /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 175         /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 176         /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 177         /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 178         /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 179         /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 180         /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 181         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 182         /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 183         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 184         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 185         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 186         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 187         /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 188         /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 189         /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 190         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 191         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 192         /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 193         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 194         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 195         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 196         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 197     }
 198 };
 199 #endif /*  CONFIG_CPM2 */
 200
 201 #define CASL_STRING1    "casl=xx"
 202 #define CASL_STRING2    "casl="
 203
 204 static const int casl_table[] = { 20, 25, 30 };
 205 #define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
 206
 207 int cas_latency(void)
 208 {
 209         char *s = getenv("serial#");
 210         int casl;
 211         int val;
 212         int i;
 213
 214         casl = CONFIG_DDR_DEFAULT_CL;
 215
 216         if (s != NULL) {
 217                 if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
 218                             strlen(CASL_STRING2)) == 0) {
 219                         val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
 220
 221                         for (i=0; i<N_CASL; ++i) {
 222                                 if (val == casl_table[i]) {
 223                                         return val;
 224                                 }
 225                         }
 226                 }
 227         }
 228
 229         return casl;
 230 }
 231
 232 int checkboard (void)
 233 {
 234         char *s = getenv("serial#");
 235
 236         printf("Board: %s", CONFIG_BOARDNAME);
 237         if (s != NULL) {
 238                 puts(", serial# ");
 239                 puts(s);
 240         }
 241         putc('\n');
 242
 243 #ifdef CONFIG_PCI
 244         printf ("PCI1:  32 bit, %d MHz (compiled)\n",
 245                 CONFIG_SYS_CLK_FREQ / 1000000);
 246 #else
 247         printf ("PCI1:  disabled\n");
 248 #endif
 249
 250         /*
 251          * Initialize local bus.
 252          */
 253         local_bus_init ();
 254
 255         return 0;
 256 }
 257
 258 int misc_init_r (void)
 259 {
 260         DECLARE_GLOBAL_DATA_PTR;
 261         volatile immap_t    *immap = (immap_t *)CFG_IMMR;
 262         volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 263
 264         /*
 265          * Adjust flash start and offset to detected values
 266          */
 267         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 268         gd->bd->bi_flashoffset = 0;
 269
 270         /*
 271          * Check if boot FLASH isn't max size
 272          */
 273         if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
 274                 memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
 275                 memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
 276
 277                 /*
 278                  * Re-check to get correct base address
 279                  */
 280                 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
 281         }
 282
 283         /*
 284          * Check if only one FLASH bank is available
 285          */
 286         if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
 287                 memctl->or1 = 0;
 288                 memctl->br1 = 0;
 289
 290                 /*
 291                  * Re-do flash protection upon new addresses
 292                  */
 293                 flash_protect (FLAG_PROTECT_CLEAR,
 294                                gd->bd->bi_flashstart, 0xffffffff,
 295                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 296
 297                 /* Monitor protection ON by default */
 298                 flash_protect (FLAG_PROTECT_SET,
 299                                CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
 300                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 301
 302                 /* Environment protection ON by default */
 303                 flash_protect (FLAG_PROTECT_SET,
 304                                CFG_ENV_ADDR,
 305                                CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
 306                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 307
 308                 /* Redundant environment protection ON by default */
 309                 flash_protect (FLAG_PROTECT_SET,
 310                                CFG_ENV_ADDR_REDUND,
 311                                CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
 312                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 313         }
 314
 315         return 0;
 316 }
 317
 318 /*
 319  * Initialize Local Bus
 320  */
 321 void local_bus_init (void)
 322 {
 323         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 324         volatile ccsr_gur_t *gur = &immap->im_gur;
 325         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
 326
 327         uint clkdiv;
 328         uint lbc_hz;
 329         sys_info_t sysinfo;
 330
 331         /*
 332          * Errata LBC11.
 333          * Fix Local Bus clock glitch when DLL is enabled.
 334          *
 335          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 336          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 337          * Between 66 and 133, the DLL is enabled with an override workaround.
 338          */
 339
 340         get_sys_info (&sysinfo);
 341         clkdiv = lbc->lcrr & 0x0f;
 342         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 343
 344         if (lbc_hz < 66) {
 345                 lbc->lcrr = CFG_LBC_LCRR | 0x80000000;  /* DLL Bypass */
 346                 lbc->ltedr = 0xa4c80000;        /* DK: !!! */
 347
 348         } else if (lbc_hz >= 133) {
 349                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);       /* DLL Enabled */
 350
 351         } else {
 352                 /*
 353                  * On REV1 boards, need to change CLKDIV before enable DLL.
 354                  * Default CLKDIV is 8, change it to 4 temporarily.
 355                  */
 356                 uint pvr = get_pvr ();
 357                 uint temp_lbcdll = 0;
 358
 359                 if (pvr == PVR_85xx_REV1) {
 360                         /* FIXME: Justify the high bit here. */
 361                         lbc->lcrr = 0x10000004;
 362                 }
 363
 364                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);       /* DLL Enabled */
 365                 udelay (200);
 366
 367                 /*
 368                  * Sample LBC DLL ctrl reg, upshift it to set the
 369                  * override bits.
 370                  */
 371                 temp_lbcdll = gur->lbcdllcr;
 372                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 373                 asm ("sync;isync;msync");
 374         }
 375 }
 376
 377 #if defined(CONFIG_PCI)
 378 /*
 379  * Initialize PCI Devices, report devices found.
 380  */
 381
 382 #ifndef CONFIG_PCI_PNP
 383 static struct pci_config_table pci_mpc85xxads_config_table[] = {
 384         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 385          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 386          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 387                                      PCI_ENET0_MEMADDR,
 388                                      PCI_COMMAND_MEMORY |
 389                                      PCI_COMMAND_MASTER}},
 390         {}
 391 };
 392 #endif
 393
 394
 395 static struct pci_controller hose = {
 396 #ifndef CONFIG_PCI_PNP
 397         config_table:pci_mpc85xxads_config_table,
 398 #endif
 399 };
 400
 401 #endif /* CONFIG_PCI */
 402
 403
 404 void pci_init_board (void)
 405 {
 406 #ifdef CONFIG_PCI
 407         extern void pci_mpc85xx_init (struct pci_controller *hose);
 408
 409         pci_mpc85xx_init (&hose);
 410 #endif /* CONFIG_PCI */
 411 }