board/tqm8xx/tqm8xx.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #if 0
  25 #define DEBUG
  26 #endif
  27
  28 #include <common.h>
  29 #include <mpc8xx.h>
  30 #ifdef CONFIG_PS2MULT
  31 #include <ps2mult.h>
  32 #endif
  33
  34 /* ------------------------------------------------------------------------- */
  35
  36 static long int dram_size (long int, long int *, long int);
  37
  38 /* ------------------------------------------------------------------------- */
  39
  40 #define _NOT_USED_      0xFFFFFFFF
  41
  42 const uint sdram_table[] =
  43 {
  44         /*
  45          * Single Read. (Offset 0 in UPMA RAM)
  46          */
  47         0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
  48         0x1FF5FC47, /* last */
  49         /*
  50          * SDRAM Initialization (offset 5 in UPMA RAM)
  51          *
  52          * This is no UPM entry point. The following definition uses
  53          * the remaining space to establish an initialization
  54          * sequence, which is executed by a RUN command.
  55          *
  56          */
  57                     0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
  58         /*
  59          * Burst Read. (Offset 8 in UPMA RAM)
  60          */
  61         0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
  62         0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
  63         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  64         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  65         /*
  66          * Single Write. (Offset 18 in UPMA RAM)
  67          */
  68         0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
  69         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  70         /*
  71          * Burst Write. (Offset 20 in UPMA RAM)
  72          */
  73         0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
  74         0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
  75                                             _NOT_USED_,
  76         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  77         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  78         /*
  79          * Refresh  (Offset 30 in UPMA RAM)
  80          */
  81         0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  82         0xFFFFFC84, 0xFFFFFC07, /* last */
  83                                 _NOT_USED_, _NOT_USED_,
  84         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  85         /*
  86          * Exception. (Offset 3c in UPMA RAM)
  87          */
  88         0x7FFFFC07, /* last */
  89                     _NOT_USED_, _NOT_USED_, _NOT_USED_,
  90 };
  91
  92 /* ------------------------------------------------------------------------- */
  93
  94
  95 /*
  96  * Check Board Identity:
  97  *
  98  * Test TQ ID string (TQM8xx...)
  99  * If present, check for "L" type (no second DRAM bank),
 100  * otherwise "L" type is assumed as default.
 101  *
 102  * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
 103  */
 104
 105 int checkboard (void)
 106 {
 107         DECLARE_GLOBAL_DATA_PTR;
 108
 109         char *s = getenv ("serial#");
 110
 111         puts ("Board: ");
 112
 113         if (!s || strncmp (s, "TQM8", 4)) {
 114                 puts ("### No HW ID - assuming TQM8xxL\n");
 115                 return (0);
 116         }
 117
 118         if ((*(s + 6) == 'L')) {        /* a TQM8xxL type */
 119                 gd->board_type = 'L';
 120         }
 121
 122         if ((*(s + 6) == 'M')) {        /* a TQM8xxM type */
 123                 gd->board_type = 'M';
 124         }
 125
 126         for (; *s; ++s) {
 127                 if (*s == ' ')
 128                         break;
 129                 putc (*s);
 130         }
 131         putc ('\n');
 132
 133         return (0);
 134 }
 135
 136 /* ------------------------------------------------------------------------- */
 137
 138 long int initdram (int board_type)
 139 {
 140         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 141         volatile memctl8xx_t *memctl = &immap->im_memctl;
 142         long int size8, size9, size10;
 143         long int size_b0 = 0;
 144         long int size_b1 = 0;
 145
 146         upmconfig (UPMA, (uint *) sdram_table,
 147                            sizeof (sdram_table) / sizeof (uint));
 148
 149         /*
 150          * Preliminary prescaler for refresh (depends on number of
 151          * banks): This value is selected for four cycles every 62.4 us
 152          * with two SDRAM banks or four cycles every 31.2 us with one
 153          * bank. It will be adjusted after memory sizing.
 154          */
 155         memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
 156
 157         /*
 158          * The following value is used as an address (i.e. opcode) for
 159          * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
 160          * the port size is 32bit the SDRAM does NOT "see" the lower two
 161          * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
 162          * MICRON SDRAMs:
 163          * ->    0 00 010 0 010
 164          *       |  |   | |   +- Burst Length = 4
 165          *       |  |   | +----- Burst Type   = Sequential
 166          *       |  |   +------- CAS Latency  = 2
 167          *       |  +----------- Operating Mode = Standard
 168          *       +-------------- Write Burst Mode = Programmed Burst Length
 169          */
 170         memctl->memc_mar = 0x00000088;
 171
 172         /*
 173          * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
 174          * preliminary addresses - these have to be modified after the
 175          * SDRAM size has been determined.
 176          */
 177         memctl->memc_or2 = CFG_OR2_PRELIM;
 178         memctl->memc_br2 = CFG_BR2_PRELIM;
 179
 180 #ifndef CONFIG_CAN_DRIVER
 181         if ((board_type != 'L') &&
 182             (board_type != 'M') ) {     /* "L" and "M" type boards have only one bank SDRAM */
 183                 memctl->memc_or3 = CFG_OR3_PRELIM;
 184                 memctl->memc_br3 = CFG_BR3_PRELIM;
 185         }
 186 #endif                                                  /* CONFIG_CAN_DRIVER */
 187
 188         memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
 189
 190         udelay (200);
 191
 192         /* perform SDRAM initializsation sequence */
 193
 194         memctl->memc_mcr = 0x80004105;  /* SDRAM bank 0 */
 195         udelay (1);
 196         memctl->memc_mcr = 0x80004230;  /* SDRAM bank 0 - execute twice */
 197         udelay (1);
 198
 199 #ifndef CONFIG_CAN_DRIVER
 200         if ((board_type != 'L') &&
 201             (board_type != 'M') ) {     /* "L" and "M" type boards have only one bank SDRAM */
 202                 memctl->memc_mcr = 0x80006105;  /* SDRAM bank 1 */
 203                 udelay (1);
 204                 memctl->memc_mcr = 0x80006230;  /* SDRAM bank 1 - execute twice */
 205                 udelay (1);
 206         }
 207 #endif                                                  /* CONFIG_CAN_DRIVER */
 208
 209         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 210
 211         udelay (1000);
 212
 213         /*
 214          * Check Bank 0 Memory Size for re-configuration
 215          *
 216          * try 8 column mode
 217          */
 218         size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
 219                                            SDRAM_MAX_SIZE);
 220         debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
 221
 222         udelay (1000);
 223
 224         /*
 225          * try 9 column mode
 226          */
 227         size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
 228                                            SDRAM_MAX_SIZE);
 229         debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
 230
 231         udelay(1000);
 232
 233 #if defined(CFG_MAMR_10COL)
 234         /*
 235          * try 10 column mode
 236          */
 237         size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
 238                                              SDRAM_MAX_SIZE);
 239         debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
 240 #else
 241         size10 = 0;
 242 #endif /* CFG_MAMR_10COL */
 243
 244         if ((size8 < size10) && (size9 < size10)) {
 245                 size_b0 = size10;
 246         } else if ((size8 < size9) && (size10 < size9)) {
 247                 size_b0 = size9;
 248                 memctl->memc_mamr = CFG_MAMR_9COL;
 249                 udelay (500);
 250         } else {
 251                 size_b0 = size8;
 252                 memctl->memc_mamr = CFG_MAMR_8COL;
 253                 udelay (500);
 254         }
 255         debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
 256
 257 #ifndef CONFIG_CAN_DRIVER
 258         if ((board_type != 'L') &&
 259             (board_type != 'M') ) {     /* "L" and "M" type boards have only one bank SDRAM */
 260                 /*
 261                  * Check Bank 1 Memory Size
 262                  * use current column settings
 263                  * [9 column SDRAM may also be used in 8 column mode,
 264                  *  but then only half the real size will be used.]
 265                  */
 266                 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
 267                                      SDRAM_MAX_SIZE);
 268                 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
 269         } else {
 270                 size_b1 = 0;
 271         }
 272 #endif  /* CONFIG_CAN_DRIVER */
 273
 274         udelay (1000);
 275
 276         /*
 277          * Adjust refresh rate depending on SDRAM type, both banks
 278          * For types > 128 MBit leave it at the current (fast) rate
 279          */
 280         if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 281                 /* reduce to 15.6 us (62.4 us / quad) */
 282                 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
 283                 udelay (1000);
 284         }
 285
 286         /*
 287          * Final mapping: map bigger bank first
 288          */
 289         if (size_b1 > size_b0) {        /* SDRAM Bank 1 is bigger - map first   */
 290
 291                 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 292                 memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 293
 294                 if (size_b0 > 0) {
 295                         /*
 296                          * Position Bank 0 immediately above Bank 1
 297                          */
 298                         memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 299                         memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 300                                            + size_b1;
 301                 } else {
 302                         unsigned long reg;
 303
 304                         /*
 305                          * No bank 0
 306                          *
 307                          * invalidate bank
 308                          */
 309                         memctl->memc_br2 = 0;
 310
 311                         /* adjust refresh rate depending on SDRAM type, one bank */
 312                         reg = memctl->memc_mptpr;
 313                         reg >>= 1;                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
 314                         memctl->memc_mptpr = reg;
 315                 }
 316
 317         } else {                                        /* SDRAM Bank 0 is bigger - map first   */
 318
 319                 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 320                 memctl->memc_br2 =
 321                                 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 322
 323                 if (size_b1 > 0) {
 324                         /*
 325                          * Position Bank 1 immediately above Bank 0
 326                          */
 327                         memctl->memc_or3 =
 328                                         ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 329                         memctl->memc_br3 =
 330                                         ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 331                                         + size_b0;
 332                 } else {
 333                         unsigned long reg;
 334
 335 #ifndef CONFIG_CAN_DRIVER
 336                         /*
 337                          * No bank 1
 338                          *
 339                          * invalidate bank
 340                          */
 341                         memctl->memc_br3 = 0;
 342 #endif                                                  /* CONFIG_CAN_DRIVER */
 343
 344                         /* adjust refresh rate depending on SDRAM type, one bank */
 345                         reg = memctl->memc_mptpr;
 346                         reg >>= 1;                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
 347                         memctl->memc_mptpr = reg;
 348                 }
 349         }
 350
 351         udelay (10000);
 352
 353 #ifdef  CONFIG_CAN_DRIVER
 354         /* Initialize OR3 / BR3 */
 355         memctl->memc_or3 = CFG_OR3_CAN;
 356         memctl->memc_br3 = CFG_BR3_CAN;
 357
 358         /* Initialize MBMR */
 359         memctl->memc_mbmr = MBMR_GPL_B4DIS;     /* GPL_B4 ouput line Disable */
 360
 361         /* Initialize UPMB for CAN: single read */
 362         memctl->memc_mdr = 0xFFFFC004;
 363         memctl->memc_mcr = 0x0100 | UPMB;
 364
 365         memctl->memc_mdr = 0x0FFFD004;
 366         memctl->memc_mcr = 0x0101 | UPMB;
 367
 368         memctl->memc_mdr = 0x0FFFC000;
 369         memctl->memc_mcr = 0x0102 | UPMB;
 370
 371         memctl->memc_mdr = 0x3FFFC004;
 372         memctl->memc_mcr = 0x0103 | UPMB;
 373
 374         memctl->memc_mdr = 0xFFFFDC05;
 375         memctl->memc_mcr = 0x0104 | UPMB;
 376
 377         /* Initialize UPMB for CAN: single write */
 378         memctl->memc_mdr = 0xFFFCC004;
 379         memctl->memc_mcr = 0x0118 | UPMB;
 380
 381         memctl->memc_mdr = 0xCFFCD004;
 382         memctl->memc_mcr = 0x0119 | UPMB;
 383
 384         memctl->memc_mdr = 0x0FFCC000;
 385         memctl->memc_mcr = 0x011A | UPMB;
 386
 387         memctl->memc_mdr = 0x7FFCC004;
 388         memctl->memc_mcr = 0x011B | UPMB;
 389
 390         memctl->memc_mdr = 0xFFFDCC05;
 391         memctl->memc_mcr = 0x011C | UPMB;
 392 #endif                                                  /* CONFIG_CAN_DRIVER */
 393
 394 #ifdef  CONFIG_ISP1362_USB
 395         /* Initialize OR5 / BR5 */
 396         memctl->memc_or5 = CFG_OR5_ISP1362;
 397         memctl->memc_br5 = CFG_BR5_ISP1362;
 398 #endif                                                  /* CONFIG_ISP1362_USB */
 399
 400
 401         return (size_b0 + size_b1);
 402 }
 403
 404 /* ------------------------------------------------------------------------- */
 405
 406 /*
 407  * Check memory range for valid RAM. A simple memory test determines
 408  * the actually available RAM size between addresses `base' and
 409  * `base + maxsize'. Some (not all) hardware errors are detected:
 410  * - short between address lines
 411  * - short between data lines
 412  */
 413
 414 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 415 {
 416         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 417         volatile memctl8xx_t *memctl = &immap->im_memctl;
 418
 419         memctl->memc_mamr = mamr_value;
 420
 421         return (get_ram_size(base, maxsize));
 422 }
 423
 424 /* ------------------------------------------------------------------------- */
 425
 426 #ifdef CONFIG_PS2MULT
 427
 428 #ifdef CONFIG_HMI10
 429 #define BASE_BAUD ( 1843200 / 16 )
 430 struct serial_state rs_table[] = {
 431         { BASE_BAUD, 4,  (void*)0xec140000 },
 432         { BASE_BAUD, 2,  (void*)0xec150000 },
 433         { BASE_BAUD, 6,  (void*)0xec160000 },
 434         { BASE_BAUD, 10, (void*)0xec170000 },
 435 };
 436
 437 #ifdef CONFIG_BOARD_EARLY_INIT_R
 438 int board_early_init_r (void)
 439 {
 440         ps2mult_early_init();
 441         return (0);
 442 }
 443 #endif
 444 #endif /* CONFIG_HMI10 */
 445
 446 #endif /* CONFIG_PS2MULT */
 447
 448 /* ---------------------------------------------------------------------------- */
 449 /* HMI10 specific stuff                                                         */
 450 /* ---------------------------------------------------------------------------- */
 451 #ifdef CONFIG_HMI10
 452
 453 int misc_init_r (void)
 454 {
 455 # ifdef CONFIG_IDE_LED
 456         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 457
 458         /* Configure PA15 as output port */
 459         immap->im_ioport.iop_padir |= 0x0001;
 460         immap->im_ioport.iop_paodr |= 0x0001;
 461         immap->im_ioport.iop_papar &= ~0x0001;
 462         immap->im_ioport.iop_padat &= ~0x0001;  /* turn it off */
 463 # endif
 464         return (0);
 465 }
 466
 467 # ifdef CONFIG_IDE_LED
 468 void ide_led (uchar led, uchar status)
 469 {
 470         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 471
 472         /* We have one led for both pcmcia slots */
 473         if (status) {                           /* led on */
 474                 immap->im_ioport.iop_padat |= 0x0001;
 475         } else {
 476                 immap->im_ioport.iop_padat &= ~0x0001;
 477         }
 478 }
 479 # endif
 480 #endif  /* CONFIG_HMI10 */
 481
 482 /* ---------------------------------------------------------------------------- */
 483 /* NSCU specific stuff                                                          */
 484 /* ---------------------------------------------------------------------------- */
 485 #ifdef CONFIG_NSCU
 486
 487 int misc_init_r (void)
 488 {
 489         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 490
 491         /* wake up ethernet module */
 492         immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin       */
 493         immr->im_ioport.iop_pcdir |=  0x0004; /* output         */
 494         immr->im_ioport.iop_pcso  &= ~0x0004; /* for clarity    */
 495         immr->im_ioport.iop_pcdat |=  0x0004; /* enable         */
 496
 497         return (0);
 498 }
 499 #endif  /* CONFIG_NSCU */
 500
 501 /* ------------------------------------------------------------------------- */