board/udoo/neo/neo.c

   1 /*
   2  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
   3  * Copyright (C) Jasbir Matharu
   4  * Copyright (C) UDOO Team
   5  *
   6  * Author: Breno Lima <breno.lima@nxp.com>
   7  * Author: Francesco Montefoschi <francesco.monte@gmail.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/gpio.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/io.h>
  23 #include <asm/imx-common/mxc_i2c.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <spl.h>
  26 #include <linux/sizes.h>
  27 #include <common.h>
  28 #include <i2c.h>
  29 #include <miiphy.h>
  30 #include <netdev.h>
  31 #include <power/pmic.h>
  32 #include <power/pfuze3000_pmic.h>
  33 #include <malloc.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 enum {
  38         UDOO_NEO_TYPE_BASIC,
  39         UDOO_NEO_TYPE_BASIC_KS,
  40         UDOO_NEO_TYPE_FULL,
  41         UDOO_NEO_TYPE_EXTENDED,
  42 };
  43
  44 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  45         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  46         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  49         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  50         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |               \
  53         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  54         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |               \
  55         PAD_CTL_ODE)
  56
  57 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  58         PAD_CTL_SPEED_MED   |                                   \
  59         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  60
  61 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  62         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  63
  64 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  65         PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
  66
  67 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |  \
  68         PAD_CTL_DSE_40ohm)
  69
  70 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |              \
  71         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  72         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  73 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |     \
  74         MUX_MODE_SION)
  75
  76 int dram_init(void)
  77 {
  78         gd->ram_size = imx_ddr_size();
  79         return 0;
  80 }
  81
  82 #ifdef CONFIG_SYS_I2C_MXC
  83 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  84 /* I2C1 for PMIC */
  85 static struct i2c_pads_info i2c_pad_info1 = {
  86         .scl = {
  87                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  88                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  89                 .gp = IMX_GPIO_NR(1, 0),
  90         },
  91         .sda = {
  92                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  93                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  94                 .gp = IMX_GPIO_NR(1, 1),
  95         },
  96 };
  97 #endif
  98
  99 #ifdef CONFIG_POWER
 100 int power_init_board(void)
 101 {
 102         struct pmic *p;
 103         int ret;
 104         unsigned int reg, rev_id;
 105
 106         ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
 107         if (ret)
 108                 return ret;
 109
 110         p = pmic_get("PFUZE3000");
 111         ret = pmic_probe(p);
 112         if (ret)
 113                 return ret;
 114
 115         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 116         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 117         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 118
 119         /* disable Low Power Mode during standby mode */
 120         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 121         reg |= 0x1;
 122         ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 123         if (ret)
 124                 return ret;
 125
 126         ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
 127         if (ret)
 128                 return ret;
 129
 130         ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
 131         if (ret)
 132                 return ret;
 133
 134         ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
 135         if (ret)
 136                 return ret;
 137
 138         ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
 139         if (ret)
 140                 return ret;
 141
 142         /* set SW1A standby voltage 0.975V */
 143         pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
 144         reg &= ~0x3f;
 145         reg |= PFUZE3000_SW1AB_SETP(9750);
 146         ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 147         if (ret)
 148                 return ret;
 149
 150         /* set SW1B standby voltage 0.975V */
 151         pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
 152         reg &= ~0x3f;
 153         reg |= PFUZE3000_SW1AB_SETP(9750);
 154         ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 155         if (ret)
 156                 return ret;
 157
 158         /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
 159         pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
 160         reg &= ~0xc0;
 161         reg |= 0x40;
 162         ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
 163         if (ret)
 164                 return ret;
 165
 166         /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
 167         pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
 168         reg &= ~0xc0;
 169         reg |= 0x40;
 170         ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
 171         if (ret)
 172                 return ret;
 173
 174         /* set VDD_ARM_IN to 1.350V */
 175         pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
 176         reg &= ~0x3f;
 177         reg |= PFUZE3000_SW1AB_SETP(13500);
 178         ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
 179         if (ret)
 180                 return ret;
 181
 182         /* set VDD_SOC_IN to 1.350V */
 183         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 184         reg &= ~0x3f;
 185         reg |= PFUZE3000_SW1AB_SETP(13500);
 186         ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 187         if (ret)
 188                 return ret;
 189
 190         /* set DDR_1_5V to 1.350V */
 191         pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
 192         reg &= ~0x0f;
 193         reg |= PFUZE3000_SW3_SETP(13500);
 194         ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
 195         if (ret)
 196                 return ret;
 197
 198         /* set VGEN2_1V5 to 1.5V */
 199         pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
 200         reg &= ~0x0f;
 201         reg |= PFUZE3000_VLDO_SETP(15000);
 202         /*  enable  */
 203         reg |= 0x10;
 204         ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
 205         if (ret)
 206                 return ret;
 207
 208         return 0;
 209 }
 210 #endif
 211
 212 static iomux_v3_cfg_t const uart1_pads[] = {
 213         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 214         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 215 };
 216
 217 static iomux_v3_cfg_t const usdhc2_pads[] = {
 218         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 219         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 220         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 221         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 222         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 223         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 224         /* CD pin */
 225         MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
 226         /* Power */
 227         MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 228 };
 229
 230 static iomux_v3_cfg_t const fec1_pads[] = {
 231         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 234         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 235         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 236         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 237         MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 238         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 239         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 240         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 241         MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 242         MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 243 };
 244
 245 static iomux_v3_cfg_t const phy_control_pads[] = {
 246         /* 25MHz Ethernet PHY Clock */
 247         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
 248         MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 249 };
 250
 251 static iomux_v3_cfg_t const board_recognition_pads[] = {
 252         /*Connected to R184*/
 253         MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
 254         /*Connected to R185*/
 255         MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
 256 };
 257
 258 static iomux_v3_cfg_t const wdog_b_pad = {
 259         MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 260 };
 261
 262 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 263         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 264 };
 265
 266 static void setup_iomux_uart(void)
 267 {
 268         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 269 }
 270
 271 static int setup_fec(int fec_id)
 272 {
 273         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 274         int reg;
 275
 276         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 277                                          ARRAY_SIZE(phy_control_pads));
 278
 279         /* Reset PHY */
 280         gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
 281         udelay(10000);
 282         gpio_set_value(IMX_GPIO_NR(2, 1), 1);
 283         udelay(100);
 284
 285         reg = readl(&anatop->pll_enet);
 286         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 287         writel(reg, &anatop->pll_enet);
 288
 289         return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
 290 }
 291
 292 int board_eth_init(bd_t *bis)
 293 {
 294         uint32_t base = IMX_FEC_BASE;
 295         struct mii_dev *bus = NULL;
 296         struct phy_device *phydev = NULL;
 297         int ret;
 298
 299         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 300
 301         setup_fec(CONFIG_FEC_ENET_DEV);
 302
 303         bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
 304         if (!bus)
 305                 return -EINVAL;
 306
 307         phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
 308                                         PHY_INTERFACE_MODE_RMII);
 309         if (!phydev) {
 310                 free(bus);
 311                 return -EINVAL;
 312         }
 313
 314         ret  = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
 315         if (ret) {
 316                 free(bus);
 317                 free(phydev);
 318                 return ret;
 319         }
 320         return 0;
 321 }
 322
 323 int board_phy_config(struct phy_device *phydev)
 324 {
 325         if (phydev->drv->config)
 326                 phydev->drv->config(phydev);
 327
 328         return 0;
 329 }
 330
 331 int board_init(void)
 332 {
 333         /* Address of boot parameters */
 334         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 335
 336         /*
 337          * Because kernel set WDOG_B mux before pad with the commone pinctrl
 338          * framwork now and wdog reset will be triggered once set WDOG_B mux
 339          * with default pad setting, we set pad setting here to workaround this.
 340          * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
 341          * as GPIO mux firstly here to workaround it.
 342          */
 343         imx_iomux_v3_setup_pad(wdog_b_pad);
 344
 345         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 346         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 347                                          ARRAY_SIZE(peri_3v3_pads));
 348
 349         /* Active high for ncp692 */
 350         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 351
 352         #ifdef CONFIG_SYS_I2C_MXC
 353         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 354         #endif
 355
 356         return 0;
 357 }
 358
 359 static int get_board_value(void)
 360 {
 361         int r184, r185;
 362
 363         imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
 364                                          ARRAY_SIZE(board_recognition_pads));
 365
 366         gpio_direction_input(IMX_GPIO_NR(4, 13));
 367         gpio_direction_input(IMX_GPIO_NR(4, 0));
 368
 369         r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
 370         r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
 371
 372         /*
 373          * Machine selection -
 374          * Machine          r184,    r185
 375          * ---------------------------------
 376          * Basic              0        0
 377          * Basic Ks           0        1
 378          * Full               1        0
 379          * Extended           1        1
 380          */
 381
 382         return (r184 << 1) + r185;
 383 }
 384
 385 int board_early_init_f(void)
 386 {
 387         setup_iomux_uart();
 388
 389         return 0;
 390 }
 391
 392 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 393         {USDHC2_BASE_ADDR, 0, 4},
 394         {USDHC3_BASE_ADDR, 0, 4},
 395 };
 396
 397 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
 398 #define USDHC2_CD_GPIO  IMX_GPIO_NR(6, 2)
 399
 400 int board_mmc_getcd(struct mmc *mmc)
 401 {
 402         return !gpio_get_value(USDHC2_CD_GPIO);
 403 }
 404
 405 int board_mmc_init(bd_t *bis)
 406 {
 407         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 408         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 409         usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 410         gpio_direction_input(USDHC2_CD_GPIO);
 411         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 412
 413         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 414         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 415 }
 416
 417 static char *board_string(void)
 418 {
 419         switch (get_board_value()) {
 420         case UDOO_NEO_TYPE_BASIC:
 421                 return "BASIC";
 422         case UDOO_NEO_TYPE_BASIC_KS:
 423                 return "BASICKS";
 424         case UDOO_NEO_TYPE_FULL:
 425                 return "FULL";
 426         case UDOO_NEO_TYPE_EXTENDED:
 427                 return "EXTENDED";
 428         }
 429         return "UNDEFINED";
 430 }
 431
 432 int checkboard(void)
 433 {
 434         printf("Board: UDOO Neo %s\n", board_string());
 435         return 0;
 436 }
 437
 438 int board_late_init(void)
 439 {
 440 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 441         setenv("board_name", board_string());
 442 #endif
 443
 444         return 0;
 445 }
 446
 447 #ifdef CONFIG_SPL_BUILD
 448
 449 #include <libfdt.h>
 450 #include <asm/arch/mx6-ddr.h>
 451
 452 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 453         .dram_dqm0 = 0x00000028,
 454         .dram_dqm1 = 0x00000028,
 455         .dram_dqm2 = 0x00000028,
 456         .dram_dqm3 = 0x00000028,
 457         .dram_ras = 0x00000020,
 458         .dram_cas = 0x00000020,
 459         .dram_odt0 = 0x00000020,
 460         .dram_odt1 = 0x00000020,
 461         .dram_sdba2 = 0x00000000,
 462         .dram_sdcke0 = 0x00003000,
 463         .dram_sdcke1 = 0x00003000,
 464         .dram_sdclk_0 = 0x00000030,
 465         .dram_sdqs0 = 0x00000028,
 466         .dram_sdqs1 = 0x00000028,
 467         .dram_sdqs2 = 0x00000028,
 468         .dram_sdqs3 = 0x00000028,
 469         .dram_reset = 0x00000020,
 470 };
 471
 472 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 473         .grp_addds = 0x00000020,
 474         .grp_ddrmode_ctl = 0x00020000,
 475         .grp_ddrpke = 0x00000000,
 476         .grp_ddrmode = 0x00020000,
 477         .grp_b0ds = 0x00000028,
 478         .grp_b1ds = 0x00000028,
 479         .grp_ctlds = 0x00000020,
 480         .grp_ddr_type = 0x000c0000,
 481         .grp_b2ds = 0x00000028,
 482         .grp_b3ds = 0x00000028,
 483 };
 484
 485 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
 486         .p0_mpwldectrl0 = 0x000E000B,
 487         .p0_mpwldectrl1 = 0x000E0010,
 488         .p0_mpdgctrl0 = 0x41600158,
 489         .p0_mpdgctrl1 = 0x01500140,
 490         .p0_mprddlctl = 0x3A383E3E,
 491         .p0_mpwrdlctl = 0x3A383C38,
 492 };
 493
 494 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
 495         .p0_mpwldectrl0 = 0x001E0022,
 496         .p0_mpwldectrl1 = 0x001C0019,
 497         .p0_mpdgctrl0 = 0x41540150,
 498         .p0_mpdgctrl1 = 0x01440138,
 499         .p0_mprddlctl = 0x403E4644,
 500         .p0_mpwrdlctl = 0x3C3A4038,
 501 };
 502
 503 /* MT41K256M16 */
 504 static struct mx6_ddr3_cfg neo_mem_ddr = {
 505         .mem_speed = 1600,
 506         .density = 4,
 507         .width = 16,
 508         .banks = 8,
 509         .rowaddr = 15,
 510         .coladdr = 10,
 511         .pagesz = 2,
 512         .trcd = 1375,
 513         .trcmin = 4875,
 514         .trasmin = 3500,
 515 };
 516
 517 /* MT41K128M16 */
 518 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
 519         .mem_speed = 1600,
 520         .density = 2,
 521         .width = 16,
 522         .banks = 8,
 523         .rowaddr = 14,
 524         .coladdr = 10,
 525         .pagesz = 2,
 526         .trcd = 1375,
 527         .trcmin = 4875,
 528         .trasmin = 3500,
 529 };
 530
 531 static void ccgr_init(void)
 532 {
 533         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 534
 535         writel(0xFFFFFFFF, &ccm->CCGR0);
 536         writel(0xFFFFFFFF, &ccm->CCGR1);
 537         writel(0xFFFFFFFF, &ccm->CCGR2);
 538         writel(0xFFFFFFFF, &ccm->CCGR3);
 539         writel(0xFFFFFFFF, &ccm->CCGR4);
 540         writel(0xFFFFFFFF, &ccm->CCGR5);
 541         writel(0xFFFFFFFF, &ccm->CCGR6);
 542         writel(0xFFFFFFFF, &ccm->CCGR7);
 543 }
 544
 545 static void spl_dram_init(void)
 546 {
 547         int board = get_board_value();
 548
 549         struct mx6_ddr_sysinfo sysinfo = {
 550                 .dsize = 1, /* width of data bus: 1 = 32 bits */
 551                 .cs_density = 24,
 552                 .ncs = 1,
 553                 .cs1_mirror = 0,
 554                 .rtt_wr = 2,
 555                 .rtt_nom = 2,           /* RTT_Nom = RZQ/2 */
 556                 .walat = 1,             /* Write additional latency */
 557                 .ralat = 5,             /* Read additional latency */
 558                 .mif3_mode = 3,         /* Command prediction working mode */
 559                 .bi_on = 1,             /* Bank interleaving enabled */
 560                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 561                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 562         };
 563
 564         mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 565         if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
 566                 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
 567                              &neo_basic_mem_ddr);
 568         else
 569                 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
 570 }
 571
 572 void board_init_f(ulong dummy)
 573 {
 574         ccgr_init();
 575
 576         /* setup AIPS and disable watchdog */
 577         arch_cpu_init();
 578
 579         board_early_init_f();
 580
 581         /* setup GP timer */
 582         timer_init();
 583
 584         /* UART clocks enabled and gd valid - init serial console */
 585         preloader_console_init();
 586
 587         /* DDR initialization */
 588         spl_dram_init();
 589
 590         /* Clear the BSS. */
 591         memset(__bss_start, 0, __bss_end - __bss_start);
 592
 593         /* load/boot image from boot device */
 594         board_init_r(NULL, 0);
 595 }
 596
 597 #endif