board/w7o/w7o.c

   1 /*
   2  * (C) Copyright 2001
   3  * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include "w7o.h"
  27 #include <asm/processor.h>
  28
  29 #include "vpd.h"
  30 #include "errors.h"
  31 #include <watchdog.h>
  32
  33 unsigned long get_dram_size (void);
  34 void sdram_init(void);
  35
  36 /*
  37  * Macros to transform values
  38  * into environment strings.
  39  */
  40 #define XMK_STR(x)      #x
  41 #define MK_STR(x)       XMK_STR(x)
  42
  43 /* ------------------------------------------------------------------------- */
  44
  45 int board_early_init_f (void)
  46 {
  47 #if defined(CONFIG_W7OLMG)
  48         /*
  49          * Setup GPIO pins - reset devices.
  50          */
  51         out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
  52         out32 (PPC405GP_GPIO0_OR, 0x3E000000);  /* set output pins to default */
  53         out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
  54
  55         /*
  56          * IRQ 0-15  405GP internally generated; active high; level sensitive
  57          * IRQ 16    405GP internally generated; active low; level sensitive
  58          * IRQ 17-24 RESERVED
  59          * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
  60          * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
  61          * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
  62          * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
  63          * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
  64          * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
  65          * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
  66          */
  67         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
  68         mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
  69
  70         mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
  71         mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
  72         mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
  73         mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,
  74                                            INT0 highest priority */
  75
  76         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
  77
  78 #elif defined(CONFIG_W7OLMC)
  79         /*
  80          * Setup GPIO pins
  81          */
  82         out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
  83         out32 (PPC405GP_GPIO0_OR, 0x03800000);  /* set out pins to default */
  84         out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
  85
  86         /*
  87          * IRQ 0-15  405GP internally generated; active high; level sensitive
  88          * IRQ 16    405GP internally generated; active low; level sensitive
  89          * IRQ 17-24 RESERVED
  90          * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
  91          * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
  92          * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
  93          * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
  94          * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
  95          * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
  96          * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
  97          */
  98         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
  99         mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
 100
 101         mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
 102         mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
 103         mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
 104         mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,
 105                                            INT0 highest priority */
 106
 107         mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 108
 109 #else  /* Unknown */
 110 #    error "Unknown W7O board configuration"
 111 #endif
 112
 113         WATCHDOG_RESET ();      /* Reset the watchdog */
 114         temp_uart_init ();      /* init the uart for debug */
 115         WATCHDOG_RESET ();      /* Reset the watchdog */
 116         test_led ();            /* test the LEDs */
 117         test_sdram (get_dram_size ());  /* test the dram */
 118         log_stat (ERR_POST1);   /* log status,post1 complete */
 119         return 0;
 120 }
 121
 122
 123 /* ------------------------------------------------------------------------- */
 124
 125 /*
 126  * Check Board Identity:
 127  */
 128 int checkboard (void)
 129 {
 130         VPD vpd;
 131
 132         puts ("Board: ");
 133
 134         /* VPD data present in I2C EEPROM */
 135         if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
 136                 /*
 137                  * Known board type.
 138                  */
 139                 if (vpd.productId[0] &&
 140                     ((strncmp (vpd.productId, "GMM", 3) == 0) ||
 141                      (strncmp (vpd.productId, "CMM", 3) == 0))) {
 142
 143                         /* Output board information on startup */
 144                         printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
 145                         return (0);
 146                 }
 147         }
 148
 149         puts ("### Unknown HW ID - assuming NOTHING\n");
 150         return (0);
 151 }
 152
 153 /* ------------------------------------------------------------------------- */
 154
 155 phys_size_t initdram (int board_type)
 156 {
 157         /*
 158          * ToDo: Move the asm init routine sdram_init() to this C file,
 159          * or even better use some common ppc4xx code available
 160          * in arch/ppc/cpu/ppc4xx
 161          */
 162         sdram_init();
 163
 164         return get_dram_size ();
 165 }
 166
 167 unsigned long get_dram_size (void)
 168 {
 169         int tmp, i, regs[4];
 170         int size = 0;
 171
 172         /* Get bank Size registers */
 173         mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);    /* get bank 0 config reg */
 174         regs[0] = mfdcr (SDRAM0_CFGDATA);
 175
 176         mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);    /* get bank 1 config reg */
 177         regs[1] = mfdcr (SDRAM0_CFGDATA);
 178
 179         mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);    /* get bank 2 config reg */
 180         regs[2] = mfdcr (SDRAM0_CFGDATA);
 181
 182         mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);    /* get bank 3 config reg */
 183         regs[3] = mfdcr (SDRAM0_CFGDATA);
 184
 185         /* compute the size, add each bank if enabled */
 186         for (i = 0; i < 4; i++) {
 187                 if (regs[i] & 0x0001) { /* if enabled, */
 188                         tmp = ((regs[i] >> (31 - 14)) & 0x7);   /* get size bits */
 189                         tmp = 0x400000 << tmp;  /* Size bits X 4MB = size */
 190                         size += tmp;
 191                 }
 192         }
 193
 194         return size;
 195 }
 196
 197 int misc_init_f (void)
 198 {
 199         return 0;
 200 }
 201
 202 static void w7o_env_init (VPD * vpd)
 203 {
 204         /*
 205          * Read VPD
 206          */
 207         if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
 208                 return;
 209
 210         /*
 211          * Known board type.
 212          */
 213         if (vpd->productId[0] &&
 214             ((strncmp (vpd->productId, "GMM", 3) == 0) ||
 215              (strncmp (vpd->productId, "CMM", 3) == 0))) {
 216                 char buf[30];
 217                 char *eth;
 218                 char *serial = getenv ("serial#");
 219                 char *ethaddr = getenv ("ethaddr");
 220
 221                 /* Set 'serial#' envvar if serial# isn't set */
 222                 if (!serial) {
 223                         sprintf (buf, "%s-%ld", vpd->productId,
 224                                  vpd->serialNum);
 225                         setenv ("serial#", buf);
 226                 }
 227
 228                 /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
 229                 eth = (char *)(vpd->ethAddrs[0]);
 230                 if (ethaddr
 231                     && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
 232                         /* Now setup ethaddr */
 233                         sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
 234                                  eth[0], eth[1], eth[2], eth[3], eth[4],
 235                                  eth[5]);
 236                         setenv ("ethaddr", buf);
 237                 }
 238         }
 239 }                               /* w7o_env_init() */
 240
 241
 242 int misc_init_r (void)
 243 {
 244         VPD vpd;                /* VPD information */
 245
 246 #if defined(CONFIG_W7OLMG)
 247         unsigned long greg;     /* GPIO Register */
 248
 249         greg = in32 (PPC405GP_GPIO0_OR);
 250
 251         /*
 252          * XXX - Unreset devices - this should be moved into VxWorks driver code
 253          */
 254         greg |= 0x41800000L;    /* SAM, PHY, Galileo */
 255
 256         out32 (PPC405GP_GPIO0_OR, greg);        /* set output pins to default */
 257 #endif /* CONFIG_W7OLMG */
 258
 259         /*
 260          * Initialize W7O environment variables
 261          */
 262         w7o_env_init (&vpd);
 263
 264         /*
 265          * Initialize the FPGA(s).
 266          */
 267         if (init_fpga () == 0)
 268                 test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
 269
 270         /* More POST testing. */
 271         post2 ();
 272
 273         /* Done with hardware initialization and POST. */
 274         log_stat (ERR_POSTOK);
 275
 276         /* Call silly, fail safe boot init routine */
 277         init_fsboot ();
 278
 279         return (0);
 280 }