2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014 O.S. Systems Software LTDA.
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/boot_mode.h>
21 #include <asm/imx-common/video.h>
22 #include <asm/imx-common/sata.h>
24 #include <linux/sizes.h>
26 #include <fsl_esdhc.h>
34 DECLARE_GLOBAL_DATA_PTR
;
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
52 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
53 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
54 #define REV_DETECTION IMX_GPIO_NR(2, 28)
58 gd
->ram_size
= imx_ddr_size();
63 static iomux_v3_cfg_t
const uart1_pads
[] = {
64 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
65 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
68 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
69 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
70 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
71 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
72 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
73 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
74 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
75 /* Carrier MicroSD Card Detect */
76 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
79 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
80 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
81 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
82 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
83 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
84 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
85 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
86 /* SOM MicroSD Card Detect */
87 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
90 static iomux_v3_cfg_t
const enet_pads
[] = {
91 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
92 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
93 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
94 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
95 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
96 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
97 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
98 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
99 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
100 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
101 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
102 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
103 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
104 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
105 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
106 /* AR8031 PHY Reset */
107 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
110 static iomux_v3_cfg_t
const rev_detection_pad
[] = {
111 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
114 static void setup_iomux_uart(void)
116 SETUP_IOMUX_PADS(uart1_pads
);
119 static void setup_iomux_enet(void)
121 SETUP_IOMUX_PADS(enet_pads
);
123 /* Reset AR8031 PHY */
124 gpio_direction_output(ETH_PHY_RESET
, 0);
126 gpio_set_value(ETH_PHY_RESET
, 1);
130 static struct fsl_esdhc_cfg usdhc_cfg
[2] = {
135 int board_mmc_getcd(struct mmc
*mmc
)
137 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
140 switch (cfg
->esdhc_base
) {
141 case USDHC1_BASE_ADDR
:
142 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
144 case USDHC3_BASE_ADDR
:
145 ret
= !gpio_get_value(USDHC3_CD_GPIO
);
152 int board_mmc_init(bd_t
*bis
)
158 * Following map is done:
159 * (U-Boot device node) (Physical Port)
161 * mmc1 Carrier board MicroSD
163 for (index
= 0; index
< CONFIG_SYS_FSL_USDHC_NUM
; ++index
) {
166 SETUP_IOMUX_PADS(usdhc3_pads
);
167 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
168 usdhc_cfg
[0].max_bus_width
= 4;
169 gpio_direction_input(USDHC3_CD_GPIO
);
172 SETUP_IOMUX_PADS(usdhc1_pads
);
173 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
174 usdhc_cfg
[1].max_bus_width
= 4;
175 gpio_direction_input(USDHC1_CD_GPIO
);
178 printf("Warning: you configured more USDHC controllers"
179 "(%d) then supported by the board (%d)\n",
180 index
+ 1, CONFIG_SYS_FSL_USDHC_NUM
);
184 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[index
]);
192 #if defined(CONFIG_VIDEO_IPUV3)
193 struct i2c_pads_info mx6q_i2c2_pad_info
= {
195 .i2c_mode
= MX6Q_PAD_KEY_COL3__I2C2_SCL
196 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
197 .gpio_mode
= MX6Q_PAD_KEY_COL3__GPIO4_IO12
198 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
199 .gp
= IMX_GPIO_NR(4, 12)
202 .i2c_mode
= MX6Q_PAD_KEY_ROW3__I2C2_SDA
203 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
204 .gpio_mode
= MX6Q_PAD_KEY_ROW3__GPIO4_IO13
205 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
206 .gp
= IMX_GPIO_NR(4, 13)
210 struct i2c_pads_info mx6dl_i2c2_pad_info
= {
212 .i2c_mode
= MX6DL_PAD_KEY_COL3__I2C2_SCL
213 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
214 .gpio_mode
= MX6DL_PAD_KEY_COL3__GPIO4_IO12
215 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
216 .gp
= IMX_GPIO_NR(4, 12)
219 .i2c_mode
= MX6DL_PAD_KEY_ROW3__I2C2_SDA
220 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
221 .gpio_mode
= MX6DL_PAD_KEY_ROW3__GPIO4_IO13
222 | MUX_PAD_CTRL(I2C_PAD_CTRL
),
223 .gp
= IMX_GPIO_NR(4, 13)
227 static iomux_v3_cfg_t
const fwadapt_7wvga_pads
[] = {
228 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK
),
229 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02
), /* HSync */
230 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03
), /* VSync */
231 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04
| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm
)), /* Contrast */
232 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15
), /* DISP0_DRDY */
233 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00
),
234 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01
),
235 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02
),
236 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03
),
237 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04
),
238 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05
),
239 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06
),
240 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07
),
241 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08
),
242 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09
),
243 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10
),
244 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11
),
245 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12
),
246 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13
),
247 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14
),
248 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15
),
249 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16
),
250 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17
),
251 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10
| MUX_PAD_CTRL(NO_PAD_CTRL
)), /* DISP0_BKLEN */
252 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| MUX_PAD_CTRL(NO_PAD_CTRL
)), /* DISP0_VDDEN */
255 static void do_enable_hdmi(struct display_info_t
const *dev
)
257 imx_enable_hdmi_phy();
260 static int detect_i2c(struct display_info_t
const *dev
)
262 return (0 == i2c_set_bus_num(dev
->bus
)) &&
263 (0 == i2c_probe(dev
->addr
));
266 static void enable_fwadapt_7wvga(struct display_info_t
const *dev
)
268 SETUP_IOMUX_PADS(fwadapt_7wvga_pads
);
270 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
271 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
274 struct display_info_t
const displays
[] = {{
277 .pixfmt
= IPU_PIX_FMT_RGB24
,
278 .detect
= detect_hdmi
,
279 .enable
= do_enable_hdmi
,
293 .vmode
= FB_VMODE_NONINTERLACED
297 .pixfmt
= IPU_PIX_FMT_RGB666
,
298 .detect
= detect_i2c
,
299 .enable
= enable_fwadapt_7wvga
,
301 .name
= "FWBADAPT-LCD-F07A-0102",
313 .vmode
= FB_VMODE_NONINTERLACED
315 size_t display_count
= ARRAY_SIZE(displays
);
317 static void setup_display(void)
319 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
325 reg
= readl(&mxc_ccm
->chsccdr
);
326 reg
|= (CHSCCDR_CLK_SEL_LDB_DI0
327 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
);
328 writel(reg
, &mxc_ccm
->chsccdr
);
330 /* Disable LCD backlight */
331 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20
);
332 gpio_direction_input(IMX_GPIO_NR(4, 20));
334 #endif /* CONFIG_VIDEO_IPUV3 */
336 int board_eth_init(bd_t
*bis
)
340 return cpu_eth_init(bis
);
343 int board_early_init_f(void)
346 #if defined(CONFIG_VIDEO_IPUV3)
349 #ifdef CONFIG_CMD_SATA
350 /* Only mx6q wandboard has SATA */
351 if (is_cpu_type(MXC_CPU_MX6Q
))
359 * Do not overwrite the console
360 * Use always serial for U-Boot console
362 int overwrite_console(void)
367 #ifdef CONFIG_CMD_BMODE
368 static const struct boot_mode board_boot_modes
[] = {
369 /* 4 bit bus width */
370 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
371 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
376 static bool is_revc1(void)
378 SETUP_IOMUX_PADS(rev_detection_pad
);
379 gpio_direction_input(REV_DETECTION
);
381 if (gpio_get_value(REV_DETECTION
))
387 int board_late_init(void)
389 #ifdef CONFIG_CMD_BMODE
390 add_board_boot_modes(board_boot_modes
);
393 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
395 setenv("board_rev", "MX6Q");
397 setenv("board_rev", "MX6DL");
400 setenv("board_name", "C1");
402 setenv("board_name", "B1");
409 /* address of boot parameters */
410 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
412 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c2_pad_info
);
414 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c2_pad_info
);
416 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c2_pad_info
);
424 puts("Board: Wandboard rev C1\n");
426 puts("Board: Wandboard rev B1\n");