board/warp7/warp7.c

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/imx-common/iomux-v3.h>
  14 #include <asm/imx-common/mxc_i2c.h>
  15 #include <asm/io.h>
  16 #include <common.h>
  17 #include <fsl_esdhc.h>
  18 #include <i2c.h>
  19 #include <mmc.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <usb.h>
  22 #include <power/pmic.h>
  23 #include <power/pfuze3000_pmic.h>
  24 #include "../freescale/common/pfuze.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
  29                         PAD_CTL_HYS)
  30 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |     \
  31                         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  32
  33 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  34         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  35
  36 #ifdef CONFIG_SYS_I2C_MXC
  37 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  38 /* I2C1 for PMIC */
  39 static struct i2c_pads_info i2c_pad_info1 = {
  40         .scl = {
  41                 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
  42                 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
  43                 .gp = IMX_GPIO_NR(4, 8),
  44         },
  45         .sda = {
  46                 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
  47                 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
  48                 .gp = IMX_GPIO_NR(4, 9),
  49         },
  50 };
  51 #endif
  52
  53 int dram_init(void)
  54 {
  55         gd->ram_size = PHYS_SDRAM_SIZE;
  56
  57         return 0;
  58 }
  59
  60 static iomux_v3_cfg_t const wdog_pads[] = {
  61         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  62 };
  63
  64 static iomux_v3_cfg_t const uart1_pads[] = {
  65         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  66         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  67 };
  68
  69 static iomux_v3_cfg_t const usdhc3_pads[] = {
  70         MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81 };
  82
  83 static void setup_iomux_uart(void)
  84 {
  85         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  86 };
  87
  88 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  89         {USDHC3_BASE_ADDR},
  90 };
  91
  92 int board_mmc_getcd(struct mmc *mmc)
  93 {
  94                 /* Assume uSDHC3 emmc is always present */
  95                 return 1;
  96 }
  97
  98 int board_mmc_init(bd_t *bis)
  99 {
 100         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 101         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 102
 103         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 104 }
 105
 106 int board_early_init_f(void)
 107 {
 108         setup_iomux_uart();
 109
 110         return 0;
 111 }
 112
 113 #ifdef CONFIG_POWER
 114 #define I2C_PMIC       0
 115 static struct pmic *pfuze;
 116 int power_init_board(void)
 117 {
 118         int ret;
 119         unsigned int reg, rev_id;
 120
 121         ret = power_pfuze3000_init(I2C_PMIC);
 122         if (ret)
 123                 return ret;
 124
 125         pfuze = pmic_get("PFUZE3000");
 126         ret = pmic_probe(pfuze);
 127         if (ret)
 128                 return ret;
 129
 130         pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
 131         pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
 132         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 133
 134         /* disable Low Power Mode during standby mode */
 135         pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
 136
 137         return 0;
 138 }
 139 #endif
 140
 141 int board_init(void)
 142 {
 143         /* address of boot parameters */
 144         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 145
 146         #ifdef CONFIG_SYS_I2C_MXC
 147                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 148         #endif
 149
 150         return 0;
 151 }
 152
 153 int checkboard(void)
 154 {
 155         char *mode;
 156
 157         if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
 158                 mode = "secure";
 159         else
 160                 mode = "non-secure";
 161
 162         printf("Board: WARP7 in %s mode\n", mode);
 163
 164         return 0;
 165 }
 166
 167 int board_usb_phy_mode(int port)
 168 {
 169         return USB_INIT_DEVICE;
 170 }
 171
 172 int board_late_init(void)
 173 {
 174         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 175
 176         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 177
 178         set_wdog_reset(wdog);
 179
 180         /*
 181          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 182          * since we use PMIC_PWRON to reset the board.
 183          */
 184         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 185
 186         return 0;
 187 }