board/xes/xpedite1000/xpedite1000.c

   1 /*
   2  * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26 #include <i2c.h>
  27 #include <net.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int board_early_init_f(void)
  32 {
  33         unsigned long sdrreg;
  34
  35         /*
  36          * Enable GPIO for pins 18 - 24
  37          * 18 = SEEPROM_WP
  38          * 19 = #M_RST
  39          * 20 = #MONARCH
  40          * 21 = #LED_ALARM
  41          * 22 = #LED_ACT
  42          * 23 = #LED_STATUS1
  43          * 24 = #LED_STATUS2
  44          */
  45         mfsdr(SDR0_PFC0, sdrreg);
  46         mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
  47         out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
  48         LED0_OFF();
  49         LED1_OFF();
  50         LED2_OFF();
  51         LED3_OFF();
  52
  53         /* Setup the external bus controller/chip selects */
  54         mtebc(PB0AP, 0x04055200);       /* 16MB Strata FLASH */
  55         mtebc(PB0CR, 0xff098000);       /* BAS=0xff0 16MB R/W 8-bit */
  56         mtebc(PB1AP, 0x04055200);       /* 512KB Socketed AMD FLASH */
  57         mtebc(PB1CR, 0xfe018000);       /* BAS=0xfe0 1MB R/W 8-bit */
  58         mtebc(PB6AP, 0x05006400);       /* 32-64MB AMD MirrorBit FLASH */
  59         mtebc(PB6CR, 0xf00da000);       /* BAS=0xf00 64MB R/W i6-bit */
  60         mtebc(PB7AP, 0x05006400);       /* 32-64MB AMD MirrorBit FLASH */
  61         mtebc(PB7CR, 0xf40da000);       /* BAS=0xf40 64MB R/W 16-bit */
  62
  63         /*
  64          * Setup the interrupt controller polarities, triggers, etc.
  65          *
  66          * Because of the interrupt handling rework to handle 440GX interrupts
  67          * with the common code, we needed to change names of the UIC registers.
  68          * Here the new relationship:
  69          *
  70          * U-Boot name  440GX name
  71          * -----------------------
  72          * UIC0         UICB0
  73          * UIC1         UIC0
  74          * UIC2         UIC1
  75          * UIC3         UIC2
  76          */
  77         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  78         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  79         mtdcr(UIC1CR, 0x00000003);      /* SMI & UIC1 crit are critical */
  80         mtdcr(UIC1PR, 0xfffffe00);      /* per ref-board manual */
  81         mtdcr(UIC1TR, 0x01c00000);      /* per ref-board manual */
  82         mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
  83         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  84
  85         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  86         mtdcr(UIC2ER, 0x00000000);      /* disable all */
  87         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
  88         mtdcr(UIC2PR, 0xffffc0ff);      /* per ref-board manual */
  89         mtdcr(UIC2TR, 0x00ff8000);      /* per ref-board manual */
  90         mtdcr(UIC2VR, 0x00000001);      /* int31 highest, base=0x000 */
  91         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  92
  93         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
  94         mtdcr(UIC3ER, 0x00000000);      /* disable all */
  95         mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
  96         mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
  97         mtdcr(UIC3TR, 0x00ff8c0f);      /* per ref-board manual */
  98         mtdcr(UIC3VR, 0x00000001);      /* int31 highest, base=0x000 */
  99         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
 100
 101         mtdcr(UIC0SR, 0xfc000000);      /* clear all */
 102         mtdcr(UIC0ER, 0x00000000);      /* disable all */
 103         mtdcr(UIC0CR, 0x00000000);      /* all non-critical */
 104         mtdcr(UIC0PR, 0xfc000000);      /* */
 105         mtdcr(UIC0TR, 0x00000000);      /* */
 106         mtdcr(UIC0VR, 0x00000001);      /* */
 107
 108         LED0_ON();
 109
 110         return 0;
 111 }
 112
 113 int checkboard(void)
 114 {
 115         char *s;
 116
 117         printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
 118         printf("       ");
 119         s = getenv("board_rev");
 120         if (s)
 121                 printf("Rev %s, ", s);
 122         s = getenv("serial#");
 123         if (s)
 124                 printf("Serial# %s, ", s);
 125         s = getenv("board_cfg");
 126         if (s)
 127                 printf("Cfg %s", s);
 128         printf("\n");
 129
 130         return 0;
 131 }
 132
 133 phys_size_t initdram(int board_type)
 134 {
 135         return spd_sdram();
 136 }
 137
 138 /*
 139  * This routine is called just prior to registering the hose and gives
 140  * the board the opportunity to check things. Returning a value of zero
 141  * indicates that things are bad & PCI initialization should be aborted.
 142  *
 143  * Different boards may wish to customize the pci controller structure
 144  * (add regions, override default access routines, etc) or perform
 145  * certain pre-initialization actions.
 146  */
 147
 148 #if defined(CONFIG_PCI)
 149 int pci_pre_init(struct pci_controller * hose)
 150 {
 151         unsigned long strap;
 152
 153         /* See if we're supposed to setup the pci */
 154         mfsdr(SDR0_SDSTP1, strap);
 155         if ((strap & 0x00010000) == 0)
 156                 return 0;
 157
 158 #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
 159         /* Setup System Device Register PCIL0_XCR */
 160         mfsdr(SDR0_XCR, strap);
 161         strap &= 0x0f000000;
 162         mtsdr(SDR0_XCR, strap);
 163 #endif
 164
 165         return 1;
 166 }
 167 #endif /* defined(CONFIG_PCI) */
 168
 169 #if defined(CONFIG_PCI)
 170 /*
 171  * Override weak is_pci_host()
 172  *
 173  * This routine is called to determine if a pci scan should be
 174  * performed. With various hardware environments (especially cPCI and
 175  * PPMC) it's insufficient to depend on the state of the arbiter enable
 176  * bit in the strap register, or generic host/adapter assumptions.
 177  *
 178  * Rather than hard-code a bad assumption in the general 440 code, the
 179  * 440 pci code requires the board to decide at runtime.
 180  *
 181  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 182  */
 183 int is_pci_host(struct pci_controller *hose)
 184 {
 185         return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
 186 }
 187 #endif /* defined(CONFIG_PCI) */
 188
 189 #ifdef CONFIG_POST
 190 /*
 191  * Returns 1 if keys pressed to start the power-on long-running tests
 192  * Called from board_init_f().
 193  */
 194 int post_hotkeys_pressed(void)
 195 {
 196         return ctrlc();
 197 }
 198
 199 void post_word_store(ulong a)
 200 {
 201         volatile ulong *save_addr =
 202                 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
 203
 204         *save_addr = a;
 205 }
 206
 207 ulong post_word_load(void)
 208 {
 209         volatile ulong *save_addr =
 210                 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
 211
 212         return *save_addr;
 213 }
 214 #endif