board/xilinx/zynq/board.c

   1 /*
   2  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <netdev.h>
  25 #include <zynqpl.h>
  26 #include <asm/arch/hardware.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #ifdef CONFIG_FPGA
  32 Xilinx_desc fpga;
  33
  34 /* It can be done differently */
  35 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  36 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  37 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  38 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  39 #endif
  40
  41 int board_init(void)
  42 {
  43 #ifdef CONFIG_FPGA
  44         u32 idcode;
  45
  46         idcode = zynq_slcr_get_idcode();
  47
  48         switch (idcode) {
  49         case XILINX_ZYNQ_7010:
  50                 fpga = fpga010;
  51                 break;
  52         case XILINX_ZYNQ_7020:
  53                 fpga = fpga020;
  54                 break;
  55         case XILINX_ZYNQ_7030:
  56                 fpga = fpga030;
  57                 break;
  58         case XILINX_ZYNQ_7045:
  59                 fpga = fpga045;
  60                 break;
  61         }
  62 #endif
  63
  64         icache_enable();
  65
  66 #ifdef CONFIG_FPGA
  67         fpga_init();
  68         fpga_add(fpga_xilinx, &fpga);
  69 #endif
  70
  71         return 0;
  72 }
  73
  74
  75 #ifdef CONFIG_CMD_NET
  76 int board_eth_init(bd_t *bis)
  77 {
  78         u32 ret = 0;
  79
  80 #if defined(CONFIG_ZYNQ_GEM)
  81 # if defined(CONFIG_ZYNQ_GEM0)
  82         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
  83                                                 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
  84 # endif
  85 # if defined(CONFIG_ZYNQ_GEM1)
  86         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
  87                                                 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
  88 # endif
  89 #endif
  90         return ret;
  91 }
  92 #endif
  93
  94 #ifdef CONFIG_CMD_MMC
  95 int board_mmc_init(bd_t *bd)
  96 {
  97         int ret = 0;
  98
  99 #if defined(CONFIG_ZYNQ_SDHCI)
 100 # if defined(CONFIG_ZYNQ_SDHCI0)
 101         ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
 102 # endif
 103 # if defined(CONFIG_ZYNQ_SDHCI1)
 104         ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
 105 # endif
 106 #endif
 107         return ret;
 108 }
 109 #endif
 110
 111 int dram_init(void)
 112 {
 113         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 114
 115         return 0;
 116 }