board/xilinx/zynq/zynq-zed/ps7_init_gpl.h

   1
   2 /******************************************************************************
   3 *
   4 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
   5 *
   6 * SPDX-License-Identifier:      GPL-2.0+
   7 *
   8 *
   9 *******************************************************************************/
  10 /****************************************************************************/
  11 /**
  12 *
  13 * @file ps7_init.h
  14 *
  15 * This file can be included in FSBL code
  16 * to get prototype of ps7_init() function
  17 * and error codes
  18 *
  19 *****************************************************************************/
  20
  21 #ifdef __cplusplus
  22 extern "C" {
  23 #endif
  24
  25
  26 //typedef unsigned int  u32;
  27
  28
  29 /** do we need to make this name more unique ? **/
  30 //extern u32 ps7_init_data[];
  31 extern unsigned long  * ps7_ddr_init_data;
  32 extern unsigned long  * ps7_mio_init_data;
  33 extern unsigned long  * ps7_pll_init_data;
  34 extern unsigned long  * ps7_clock_init_data;
  35 extern unsigned long  * ps7_peripherals_init_data;
  36
  37
  38
  39 #define OPCODE_EXIT       0U
  40 #define OPCODE_CLEAR      1U
  41 #define OPCODE_WRITE      2U
  42 #define OPCODE_MASKWRITE  3U
  43 #define OPCODE_MASKPOLL   4U
  44 #define OPCODE_MASKDELAY  5U
  45 #define NEW_PS7_ERR_CODE 1
  46
  47 /* Encode number of arguments in last nibble */
  48 #define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
  49 #define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
  50 #define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
  51 #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
  52 #define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
  53 #define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
  54
  55 /* Returns codes  of PS7_Init */
  56 #define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
  57 #define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
  58 #define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
  59 #define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
  60 #define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
  61 #define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
  62
  63
  64 /* Silicon Versions */
  65 #define PCW_SILICON_VERSION_1 0
  66 #define PCW_SILICON_VERSION_2 1
  67 #define PCW_SILICON_VERSION_3 2
  68
  69 /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
  70 #define PS7_POST_CONFIG
  71
  72 /* Freq of all peripherals */
  73
  74 #define APU_FREQ  666666687
  75 #define DDR_FREQ  533333374
  76 #define DCI_FREQ  10158731
  77 #define QSPI_FREQ  200000000
  78 #define SMC_FREQ  10000000
  79 #define ENET0_FREQ  125000000
  80 #define ENET1_FREQ  10000000
  81 #define USB0_FREQ  60000000
  82 #define USB1_FREQ  60000000
  83 #define SDIO_FREQ  50000000
  84 #define UART_FREQ  50000000
  85 #define SPI_FREQ  10000000
  86 #define I2C_FREQ  111111115
  87 #define WDT_FREQ  111111115
  88 #define TTC_FREQ  50000000
  89 #define CAN_FREQ  10000000
  90 #define PCAP_FREQ  200000000
  91 #define TPIU_FREQ  200000000
  92 #define FPGA0_FREQ  100000000
  93 #define FPGA1_FREQ  142857132
  94 #define FPGA2_FREQ  50000000
  95 #define FPGA3_FREQ  50000000
  96
  97
  98 /* For delay calculation using global registers*/
  99 #define SCU_GLOBAL_TIMER_COUNT_L32      0xF8F00200
 100 #define SCU_GLOBAL_TIMER_COUNT_U32      0xF8F00204
 101 #define SCU_GLOBAL_TIMER_CONTROL        0xF8F00208
 102 #define SCU_GLOBAL_TIMER_AUTO_INC       0xF8F00218
 103
 104 int ps7_config( unsigned long*);
 105 int ps7_init();
 106 int ps7_post_config();
 107 int ps7_debug();
 108 char* getPS7MessageInfo(unsigned key);
 109
 110 void perf_start_clock(void);
 111 void perf_disable_clock(void);
 112 void perf_reset_clock(void);
 113 void perf_reset_and_start_timer();
 114 int get_number_of_cycles_for_delay(unsigned int delay);
 115 #ifdef __cplusplus
 116 }
 117 #endif