board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h

   1 /*
   2  * Copyright (c) Xilinx, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifdef __cplusplus
   8 extern "C" {
   9 #endif
  10
  11 /*typedef unsigned int  u32; */
  12
  13 /** do we need to make this name more unique ? **/
  14 /*extern u32 ps7_init_data[]; */
  15 extern unsigned long *ps7_ddr_init_data;
  16 extern unsigned long *ps7_mio_init_data;
  17 extern unsigned long *ps7_pll_init_data;
  18 extern unsigned long *ps7_clock_init_data;
  19 extern unsigned long *ps7_peripherals_init_data;
  20
  21 #define OPCODE_EXIT       0U
  22 #define OPCODE_CLEAR      1U
  23 #define OPCODE_WRITE      2U
  24 #define OPCODE_MASKWRITE  3U
  25 #define OPCODE_MASKPOLL   4U
  26 #define OPCODE_MASKDELAY  5U
  27 #define NEW_PS7_ERR_CODE 1
  28
  29 /* Encode number of arguments in last nibble */
  30 #define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
  31 #define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
  32 #define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
  33 #define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
  34 #define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
  35 #define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
  36
  37 /* Returns codes  of PS7_Init */
  38 #define PS7_INIT_SUCCESS   (0)  /* 0 is success in good old C */
  39 #define PS7_INIT_CORRUPT   (1)  /* 1 the data is corrupted, and slcr reg are in corrupted state now */
  40 #define PS7_INIT_TIMEOUT   (2)  /* 2 when a poll operation timed out */
  41 #define PS7_POLL_FAILED_DDR_INIT (3)    /* 3 when a poll operation timed out for ddr init */
  42 #define PS7_POLL_FAILED_DMA      (4)    /* 4 when a poll operation timed out for dma done bit */
  43 #define PS7_POLL_FAILED_PLL      (5)    /* 5 when a poll operation timed out for pll sequence init */
  44
  45 /* Silicon Versions */
  46 #define PCW_SILICON_VERSION_1 0
  47 #define PCW_SILICON_VERSION_2 1
  48 #define PCW_SILICON_VERSION_3 2
  49
  50 /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
  51 #define PS7_POST_CONFIG
  52
  53 /* Freq of all peripherals */
  54
  55 #define APU_FREQ  650000000
  56 #define DDR_FREQ  525000000
  57 #define DCI_FREQ  10096154
  58 #define QSPI_FREQ  200000000
  59 #define SMC_FREQ  10000000
  60 #define ENET0_FREQ  125000000
  61 #define ENET1_FREQ  10000000
  62 #define USB0_FREQ  60000000
  63 #define USB1_FREQ  60000000
  64 #define SDIO_FREQ  50000000
  65 #define UART_FREQ  100000000
  66 #define SPI_FREQ  10000000
  67 #define I2C_FREQ  108333336
  68 #define WDT_FREQ  108333336
  69 #define TTC_FREQ  50000000
  70 #define CAN_FREQ  10000000
  71 #define PCAP_FREQ  200000000
  72 #define TPIU_FREQ  200000000
  73 #define FPGA0_FREQ  100000000
  74 #define FPGA1_FREQ  142857132
  75 #define FPGA2_FREQ  200000000
  76 #define FPGA3_FREQ  50000000
  77
  78
  79 /* For delay calculation using global registers*/
  80 #define SCU_GLOBAL_TIMER_COUNT_L32      0xF8F00200
  81 #define SCU_GLOBAL_TIMER_COUNT_U32      0xF8F00204
  82 #define SCU_GLOBAL_TIMER_CONTROL        0xF8F00208
  83 #define SCU_GLOBAL_TIMER_AUTO_INC       0xF8F00218
  84
  85 int ps7_config(unsigned long *);
  86 int ps7_init(void);
  87 int ps7_post_config(void);
  88 int ps7_debug(void);
  89 char *getPS7MessageInfo(unsigned key);
  90
  91 void perf_start_clock(void);
  92 void perf_disable_clock(void);
  93 void perf_reset_clock(void);
  94 void perf_reset_and_start_timer(void);
  95 int get_number_of_cycles_for_delay(unsigned int delay);
  96 #ifdef __cplusplus
  97 }
  98 #endif