board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <usb.h>
  18 #include <dwc3-uboot.h>
  19 #include <zynqmppl.h>
  20 #include <i2c.h>
  21 #include <g_dnl.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  26     !defined(CONFIG_SPL_BUILD)
  27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  28
  29 static const struct {
  30         u32 id;
  31         u32 ver;
  32         char *name;
  33 } zynqmp_devices[] = {
  34         {
  35                 .id = 0x10,
  36                 .name = "3eg",
  37         },
  38         {
  39                 .id = 0x10,
  40                 .ver = 0x2c,
  41                 .name = "3cg",
  42         },
  43         {
  44                 .id = 0x11,
  45                 .name = "2eg",
  46         },
  47         {
  48                 .id = 0x11,
  49                 .ver = 0x2c,
  50                 .name = "2cg",
  51         },
  52         {
  53                 .id = 0x20,
  54                 .name = "5ev",
  55         },
  56         {
  57                 .id = 0x20,
  58                 .ver = 0x100,
  59                 .name = "5eg",
  60         },
  61         {
  62                 .id = 0x20,
  63                 .ver = 0x12c,
  64                 .name = "5cg",
  65         },
  66         {
  67                 .id = 0x21,
  68                 .name = "4ev",
  69         },
  70         {
  71                 .id = 0x21,
  72                 .ver = 0x100,
  73                 .name = "4eg",
  74         },
  75         {
  76                 .id = 0x21,
  77                 .ver = 0x12c,
  78                 .name = "4cg",
  79         },
  80         {
  81                 .id = 0x30,
  82                 .name = "7ev",
  83         },
  84         {
  85                 .id = 0x30,
  86                 .ver = 0x100,
  87                 .name = "7eg",
  88         },
  89         {
  90                 .id = 0x30,
  91                 .ver = 0x12c,
  92                 .name = "7cg",
  93         },
  94         {
  95                 .id = 0x38,
  96                 .name = "9eg",
  97         },
  98         {
  99                 .id = 0x38,
 100                 .ver = 0x2c,
 101                 .name = "9cg",
 102         },
 103         {
 104                 .id = 0x39,
 105                 .name = "6eg",
 106         },
 107         {
 108                 .id = 0x39,
 109                 .ver = 0x2c,
 110                 .name = "6cg",
 111         },
 112         {
 113                 .id = 0x40,
 114                 .name = "11eg",
 115         },
 116         { /* For testing purpose only */
 117                 .id = 0x50,
 118                 .ver = 0x2c,
 119                 .name = "15cg",
 120         },
 121         {
 122                 .id = 0x50,
 123                 .name = "15eg",
 124         },
 125         {
 126                 .id = 0x58,
 127                 .name = "19eg",
 128         },
 129         {
 130                 .id = 0x59,
 131                 .name = "17eg",
 132         },
 133 };
 134 #endif
 135
 136 int chip_id(unsigned char id)
 137 {
 138         struct pt_regs regs;
 139         int val = -EINVAL;
 140
 141         if (current_el() != 3) {
 142                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 143                 regs.regs[1] = 0;
 144                 regs.regs[2] = 0;
 145                 regs.regs[3] = 0;
 146
 147                 smc_call(&regs);
 148
 149                 /*
 150                  * SMC returns:
 151                  * regs[0][31:0]  = status of the operation
 152                  * regs[0][63:32] = CSU.IDCODE register
 153                  * regs[1][31:0]  = CSU.version register
 154                  * regs[1][63:32] = CSU.IDCODE2 register
 155                  */
 156                 switch (id) {
 157                 case IDCODE:
 158                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 159                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 160                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 161                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 162                         val = regs.regs[0];
 163                         break;
 164                 case VERSION:
 165                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 166                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 167                         val = regs.regs[1];
 168                         break;
 169                 case IDCODE2:
 170                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 171                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 172                         val = regs.regs[1];
 173                         break;
 174                 default:
 175                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 176                 }
 177         } else {
 178                 switch (id) {
 179                 case IDCODE:
 180                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 181                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 182                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 183                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 184                         break;
 185                 case VERSION:
 186                         val = readl(ZYNQMP_CSU_VER_ADDR);
 187                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 188                         break;
 189                 default:
 190                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 191                 }
 192         }
 193
 194         return val;
 195 }
 196
 197 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 198         !defined(CONFIG_SPL_BUILD)
 199 static char *zynqmp_get_silicon_idcode_name(void)
 200 {
 201         u32 i, id, ver;
 202
 203         id = chip_id(IDCODE);
 204         ver = chip_id(IDCODE2);
 205
 206         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 207                 if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
 208                         return zynqmp_devices[i].name;
 209         }
 210         return "unknown";
 211 }
 212 #endif
 213
 214 int board_early_init_f(void)
 215 {
 216 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 217         zynqmp_pmufw_version();
 218 #endif
 219
 220 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 221         psu_init();
 222 #endif
 223
 224         return 0;
 225 }
 226
 227 #define ZYNQMP_VERSION_SIZE     9
 228
 229 int board_init(void)
 230 {
 231         printf("EL Level:\tEL%d\n", current_el());
 232
 233 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 234     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 235     defined(CONFIG_SPL_BUILD))
 236         if (current_el() != 3) {
 237                 static char version[ZYNQMP_VERSION_SIZE];
 238
 239                 strncat(version, "xczu", 4);
 240                 zynqmppl.name = strncat(version,
 241                                         zynqmp_get_silicon_idcode_name(),
 242                                         ZYNQMP_VERSION_SIZE - 5);
 243                 printf("Chip ID:\t%s\n", zynqmppl.name);
 244                 fpga_init();
 245                 fpga_add(fpga_xilinx, &zynqmppl);
 246         }
 247 #endif
 248
 249         return 0;
 250 }
 251
 252 int board_early_init_r(void)
 253 {
 254         u32 val;
 255
 256         val = readl(&crlapb_base->timestamp_ref_ctrl);
 257         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 258
 259         if (current_el() == 3 && !val) {
 260                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 261                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 262                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 263
 264                 /* Program freq register in System counter */
 265                 writel(zynqmp_get_system_timer_freq(),
 266                        &iou_scntr_secure->base_frequency_id_register);
 267                 /* And enable system counter */
 268                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 269                        &iou_scntr_secure->counter_control_register);
 270         }
 271         return 0;
 272 }
 273
 274 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 275 {
 276 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 277     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 278     defined(CONFIG_ZYNQ_EEPROM_BUS)
 279         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 280
 281         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 282                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 283                         ethaddr, 6))
 284                 printf("I2C EEPROM MAC address read failed\n");
 285 #endif
 286
 287         return 0;
 288 }
 289
 290 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 291 int dram_init_banksize(void)
 292 {
 293         return fdtdec_setup_memory_banksize();
 294 }
 295
 296 int dram_init(void)
 297 {
 298         if (fdtdec_setup_memory_size() != 0)
 299                 return -EINVAL;
 300
 301         return 0;
 302 }
 303 #else
 304 int dram_init(void)
 305 {
 306         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 307
 308         return 0;
 309 }
 310 #endif
 311
 312 void reset_cpu(ulong addr)
 313 {
 314 }
 315
 316 int board_late_init(void)
 317 {
 318         u32 reg = 0;
 319         u8 bootmode;
 320         const char *mode;
 321         char *new_targets;
 322
 323         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 324                 debug("Saved variables - Skipping\n");
 325                 return 0;
 326         }
 327
 328         reg = readl(&crlapb_base->boot_mode);
 329         if (reg >> BOOT_MODE_ALT_SHIFT)
 330                 reg >>= BOOT_MODE_ALT_SHIFT;
 331
 332         bootmode = reg & BOOT_MODES_MASK;
 333
 334         puts("Bootmode: ");
 335         switch (bootmode) {
 336         case USB_MODE:
 337                 puts("USB_MODE\n");
 338                 mode = "usb";
 339                 break;
 340         case JTAG_MODE:
 341                 puts("JTAG_MODE\n");
 342                 mode = "pxe dhcp";
 343                 break;
 344         case QSPI_MODE_24BIT:
 345         case QSPI_MODE_32BIT:
 346                 mode = "qspi0";
 347                 puts("QSPI_MODE\n");
 348                 break;
 349         case EMMC_MODE:
 350                 puts("EMMC_MODE\n");
 351                 mode = "mmc0";
 352                 break;
 353         case SD_MODE:
 354                 puts("SD_MODE\n");
 355                 mode = "mmc0";
 356                 break;
 357         case SD1_LSHFT_MODE:
 358                 puts("LVL_SHFT_");
 359                 /* fall through */
 360         case SD_MODE1:
 361                 puts("SD_MODE1\n");
 362 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 363                 mode = "mmc1";
 364 #else
 365                 mode = "mmc0";
 366 #endif
 367                 break;
 368         case NAND_MODE:
 369                 puts("NAND_MODE\n");
 370                 mode = "nand0";
 371                 break;
 372         default:
 373                 mode = "";
 374                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 375                 break;
 376         }
 377
 378         /*
 379          * One terminating char + one byte for space between mode
 380          * and default boot_targets
 381          */
 382         new_targets = calloc(1, strlen(mode) +
 383                                 strlen(env_get("boot_targets")) + 2);
 384
 385         sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
 386         env_set("boot_targets", new_targets);
 387
 388         return 0;
 389 }
 390
 391 int checkboard(void)
 392 {
 393         puts("Board: Xilinx ZynqMP\n");
 394         return 0;
 395 }
 396
 397 #ifdef CONFIG_USB_DWC3
 398 static struct dwc3_device dwc3_device_data0 = {
 399         .maximum_speed = USB_SPEED_HIGH,
 400         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 401         .dr_mode = USB_DR_MODE_PERIPHERAL,
 402         .index = 0,
 403 };
 404
 405 static struct dwc3_device dwc3_device_data1 = {
 406         .maximum_speed = USB_SPEED_HIGH,
 407         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 408         .dr_mode = USB_DR_MODE_PERIPHERAL,
 409         .index = 1,
 410 };
 411
 412 int usb_gadget_handle_interrupts(int index)
 413 {
 414         dwc3_uboot_handle_interrupt(index);
 415         return 0;
 416 }
 417
 418 int board_usb_init(int index, enum usb_init_type init)
 419 {
 420         debug("%s: index %x\n", __func__, index);
 421
 422 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 423         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 424 #endif
 425
 426         switch (index) {
 427         case 0:
 428                 return dwc3_uboot_init(&dwc3_device_data0);
 429         case 1:
 430                 return dwc3_uboot_init(&dwc3_device_data1);
 431         };
 432
 433         return -1;
 434 }
 435
 436 int board_usb_cleanup(int index, enum usb_init_type init)
 437 {
 438         dwc3_uboot_exit(index);
 439         return 0;
 440 }
 441 #endif