board/zipitz2/zipitz2.c

   1 /*
   2  * Copyright (C) 2009
   3  * Marek Vasut <marek.vasut@gmail.com>
   4  *
   5  * Heavily based on pxa255_idp platform
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <command.h>
  12 #include <serial.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/pxa.h>
  15 #include <asm/arch/regs-mmc.h>
  16 #include <spi.h>
  17 #include <asm/io.h>
  18 #include <usb.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #ifdef  CONFIG_CMD_SPI
  23 void lcd_start(void);
  24 #else
  25 inline void lcd_start(void) {};
  26 #endif
  27
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31 int board_init(void)
  32 {
  33         /* We have RAM, disable cache */
  34         dcache_disable();
  35         icache_disable();
  36
  37         /* arch number of Z2 */
  38         gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
  39
  40         /* adress of boot parameters */
  41         gd->bd->bi_boot_params = 0xa0000100;
  42
  43         /* Enable LCD */
  44         lcd_start();
  45
  46         return 0;
  47 }
  48
  49 int dram_init(void)
  50 {
  51         pxa2xx_dram_init();
  52         gd->ram_size = PHYS_SDRAM_1_SIZE;
  53         return 0;
  54 }
  55
  56 #ifdef  CONFIG_CMD_USB
  57 int board_usb_init(int index, enum usb_init_type init)
  58 {
  59         /* enable port 2 */
  60         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  61                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  62
  63         return 0;
  64 }
  65
  66 int board_usb_cleanup(int index, enum usb_init_type init)
  67 {
  68         return 0;
  69 }
  70
  71 void usb_board_stop(void)
  72 {
  73 }
  74 #endif
  75
  76 void dram_init_banksize(void)
  77 {
  78         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  79         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  80 }
  81
  82 #ifdef  CONFIG_CMD_MMC
  83 int board_mmc_init(bd_t *bis)
  84 {
  85         pxa_mmc_register(0);
  86         return 0;
  87 }
  88 #endif
  89
  90 #ifdef  CONFIG_CMD_SPI
  91
  92 struct {
  93         unsigned char   reg;
  94         unsigned short  data;
  95         unsigned char   mdelay;
  96 } lcd_data[] = {
  97         { 0x07, 0x0000, 0 },
  98         { 0x13, 0x0000, 10 },
  99         { 0x11, 0x3004, 0 },
 100         { 0x14, 0x200F, 0 },
 101         { 0x10, 0x1a20, 0 },
 102         { 0x13, 0x0040, 50 },
 103         { 0x13, 0x0060, 0 },
 104         { 0x13, 0x0070, 200 },
 105         { 0x01, 0x0127, 0 },
 106         { 0x02, 0x0700, 0 },
 107         { 0x03, 0x1030, 0 },
 108         { 0x08, 0x0208, 0 },
 109         { 0x0B, 0x0620, 0 },
 110         { 0x0C, 0x0110, 0 },
 111         { 0x30, 0x0120, 0 },
 112         { 0x31, 0x0127, 0 },
 113         { 0x32, 0x0000, 0 },
 114         { 0x33, 0x0503, 0 },
 115         { 0x34, 0x0727, 0 },
 116         { 0x35, 0x0124, 0 },
 117         { 0x36, 0x0706, 0 },
 118         { 0x37, 0x0701, 0 },
 119         { 0x38, 0x0F00, 0 },
 120         { 0x39, 0x0F00, 0 },
 121         { 0x40, 0x0000, 0 },
 122         { 0x41, 0x0000, 0 },
 123         { 0x42, 0x013f, 0 },
 124         { 0x43, 0x0000, 0 },
 125         { 0x44, 0x013f, 0 },
 126         { 0x45, 0x0000, 0 },
 127         { 0x46, 0xef00, 0 },
 128         { 0x47, 0x013f, 0 },
 129         { 0x48, 0x0000, 0 },
 130         { 0x07, 0x0015, 30 },
 131         { 0x07, 0x0017, 0 },
 132         { 0x20, 0x0000, 0 },
 133         { 0x21, 0x0000, 0 },
 134         { 0x22, 0x0000, 0 },
 135 };
 136
 137 void zipitz2_spi_sda(int set)
 138 {
 139         /* GPIO 13 */
 140         if (set)
 141                 writel((1 << 13), GPSR0);
 142         else
 143                 writel((1 << 13), GPCR0);
 144 }
 145
 146 void zipitz2_spi_scl(int set)
 147 {
 148         /* GPIO 22 */
 149         if (set)
 150                 writel((1 << 22), GPCR0);
 151         else
 152                 writel((1 << 22), GPSR0);
 153 }
 154
 155 unsigned char zipitz2_spi_read(void)
 156 {
 157         /* GPIO 40 */
 158         return !!(readl(GPLR1) & (1 << 8));
 159 }
 160
 161 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 162 {
 163         /* Always valid */
 164         return 1;
 165 }
 166
 167 void spi_cs_activate(struct spi_slave *slave)
 168 {
 169         /* GPIO 88 low */
 170         writel((1 << 24), GPCR2);
 171 }
 172
 173 void spi_cs_deactivate(struct spi_slave *slave)
 174 {
 175         /* GPIO 88 high */
 176         writel((1 << 24), GPSR2);
 177 }
 178
 179 void lcd_start(void)
 180 {
 181         int i;
 182         unsigned char reg[3] = { 0x74, 0x00, 0 };
 183         unsigned char data[3] = { 0x76, 0, 0 };
 184         unsigned char dummy[3] = { 0, 0, 0 };
 185
 186         /* PWM2 AF */
 187         writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
 188         /* Enable clock to all PWM */
 189         writel(readl(CKEN) | 0x3, CKEN);
 190         /* Configure PWM2 */
 191         writel(0x4f, PWM_CTRL2);
 192         writel(0x2ff, PWM_PWDUTY2);
 193         writel(792, PWM_PERVAL2);
 194
 195         /* Toggle the reset pin to reset the LCD */
 196         writel((1 << 19), GPSR0);
 197         udelay(100000);
 198         writel((1 << 19), GPCR0);
 199         udelay(20000);
 200         writel((1 << 19), GPSR0);
 201         udelay(20000);
 202
 203         /* Program the LCD init sequence */
 204         for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
 205                 reg[0] = 0x74;
 206                 reg[1] = 0x0;
 207                 reg[2] = lcd_data[i].reg;
 208                 spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
 209
 210                 data[0] = 0x76;
 211                 data[1] = lcd_data[i].data >> 8;
 212                 data[2] = lcd_data[i].data & 0xff;
 213                 spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
 214
 215                 if (lcd_data[i].mdelay)
 216                         udelay(lcd_data[i].mdelay * 1000);
 217         }
 218
 219         writel((1 << 11), GPSR0);
 220 }
 221 #endif