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1 /*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * I2C Functions similar to the standard memory functions.
26 *
27 * There are several parameters in many of the commands that bear further
28 * explanations:
29 *
30 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
31 * Each I2C chip on the bus has a unique address. On the I2C data bus,
32 * the address is the upper seven bits and the LSB is the "read/write"
33 * bit. Note that the {i2c_chip} address specified on the command
34 * line is not shifted up: e.g. a typical EEPROM memory chip may have
35 * an I2C address of 0x50, but the data put on the bus will be 0xA0
36 * for write and 0xA1 for read. This "non shifted" address notation
37 * matches at least half of the data sheets :-/.
38 *
39 * {addr} is the address (or offset) within the chip. Small memory
40 * chips have 8 bit addresses. Large memory chips have 16 bit
41 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
42 * Many non-memory chips have multiple registers and {addr} is used
43 * as the register index. Some non-memory chips have only one register
44 * and therefore don't need any {addr} parameter.
45 *
46 * The default {addr} parameter is one byte (.1) which works well for
47 * memories and registers with 8 bits of address space.
48 *
49 * You can specify the length of the {addr} field with the optional .0,
50 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
51 * manipulating a single register device which doesn't use an address
52 * field, use "0.0" for the address and the ".0" length field will
53 * suppress the address in the I2C data stream. This also works for
54 * successive reads using the I2C auto-incrementing memory pointer.
55 *
56 * If you are manipulating a large memory with 2-byte addresses, use
57 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
58 *
59 * Then there are the unfortunate memory chips that spill the most
60 * significant 1, 2, or 3 bits of address into the chip address byte.
61 * This effectively makes one chip (logically) look like 2, 4, or
62 * 8 chips. This is handled (awkwardly) by #defining
63 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
64 * {addr} field (since .1 is the default, it doesn't actually have to
65 * be specified). Examples: given a memory chip at I2C chip address
66 * 0x50, the following would happen...
67 * i2c md 50 0 10 display 16 bytes starting at 0x000
68 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
69 * i2c md 50 100 10 display 16 bytes starting at 0x100
70 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
71 * i2c md 50 210 10 display 16 bytes starting at 0x210
72 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
73 * This is awfully ugly. It would be nice if someone would think up
74 * a better way of handling this.
75 *
76 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
77 */
78
79 #include <common.h>
80 #include <command.h>
81 #include <environment.h>
82 #include <i2c.h>
83 #include <malloc.h>
84 #include <asm/byteorder.h>
85
86 /* Display values from last command.
87 * Memory modify remembered values are different from display memory.
88 */
89 static uchar i2c_dp_last_chip;
90 static uint i2c_dp_last_addr;
91 static uint i2c_dp_last_alen;
92 static uint i2c_dp_last_length = 0x10;
93
94 static uchar i2c_mm_last_chip;
95 static uint i2c_mm_last_addr;
96 static uint i2c_mm_last_alen;
97
98 /* If only one I2C bus is present, the list of devices to ignore when
99 * the probe command is issued is represented by a 1D array of addresses.
100 * When multiple buses are present, the list is an array of bus-address
101 * pairs. The following macros take care of this */
102
103 #if defined(CONFIG_SYS_I2C_NOPROBES)
104 #if defined(CONFIG_I2C_MULTI_BUS)
105 static struct
106 {
107 uchar bus;
108 uchar addr;
109 } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
110 #define GET_BUS_NUM i2c_get_bus_num()
111 #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
112 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
113 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
114 #else /* single bus */
115 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
116 #define GET_BUS_NUM 0
117 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
118 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
119 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
120 #endif /* CONFIG_MULTI_BUS */
121
122 #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
123 #endif
124
125 #if defined(CONFIG_I2C_MUX)
126 static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
127 static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
128
129 DECLARE_GLOBAL_DATA_PTR;
130
131 #endif
132
133 #define DISP_LINE_LEN 16
134
135 /* implement possible board specific board init */
136 void __def_i2c_init_board(void)
137 {
138 return;
139 }
140 void i2c_init_board(void)
141 __attribute__((weak, alias("__def_i2c_init_board")));
142
143 /* TODO: Implement architecture-specific get/set functions */
144 unsigned int __def_i2c_get_bus_speed(void)
145 {
146 return CONFIG_SYS_I2C_SPEED;
147 }
148 unsigned int i2c_get_bus_speed(void)
149 __attribute__((weak, alias("__def_i2c_get_bus_speed")));
150
151 int __def_i2c_set_bus_speed(unsigned int speed)
152 {
153 if (speed != CONFIG_SYS_I2C_SPEED)
154 return -1;
155
156 return 0;
157 }
158 int i2c_set_bus_speed(unsigned int)
159 __attribute__((weak, alias("__def_i2c_set_bus_speed")));
160
161 /*
162 * get_alen: small parser helper function to get address length
163 * returns the address length
164 */
165 static uint get_alen(char *arg)
166 {
167 int j;
168 int alen;
169
170 alen = 1;
171 for (j = 0; j < 8; j++) {
172 if (arg[j] == '.') {
173 alen = arg[j+1] - '0';
174 break;
175 } else if (arg[j] == '\0')
176 break;
177 }
178 return alen;
179 }
180
181 /*
182 * Syntax:
183 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
184 */
185
186 static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
187 {
188 u_char chip;
189 uint devaddr, alen, length;
190 u_char *memaddr;
191
192 if (argc != 5)
193 return cmd_usage(cmdtp);
194
195 /*
196 * I2C chip address
197 */
198 chip = simple_strtoul(argv[1], NULL, 16);
199
200 /*
201 * I2C data address within the chip. This can be 1 or
202 * 2 bytes long. Some day it might be 3 bytes long :-).
203 */
204 devaddr = simple_strtoul(argv[2], NULL, 16);
205 alen = get_alen(argv[2]);
206 if (alen > 3)
207 return cmd_usage(cmdtp);
208
209 /*
210 * Length is the number of objects, not number of bytes.
211 */
212 length = simple_strtoul(argv[3], NULL, 16);
213
214 /*
215 * memaddr is the address where to store things in memory
216 */
217 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
218
219 if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
220 puts ("Error reading the chip.\n");
221 return 1;
222 }
223 return 0;
224 }
225
226 /*
227 * Syntax:
228 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
229 */
230 static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
231 {
232 u_char chip;
233 uint addr, alen, length;
234 int j, nbytes, linebytes;
235
236 /* We use the last specified parameters, unless new ones are
237 * entered.
238 */
239 chip = i2c_dp_last_chip;
240 addr = i2c_dp_last_addr;
241 alen = i2c_dp_last_alen;
242 length = i2c_dp_last_length;
243
244 if (argc < 3)
245 return cmd_usage(cmdtp);
246
247 if ((flag & CMD_FLAG_REPEAT) == 0) {
248 /*
249 * New command specified.
250 */
251
252 /*
253 * I2C chip address
254 */
255 chip = simple_strtoul(argv[1], NULL, 16);
256
257 /*
258 * I2C data address within the chip. This can be 1 or
259 * 2 bytes long. Some day it might be 3 bytes long :-).
260 */
261 addr = simple_strtoul(argv[2], NULL, 16);
262 alen = get_alen(argv[2]);
263 if (alen > 3)
264 return cmd_usage(cmdtp);
265
266 /*
267 * If another parameter, it is the length to display.
268 * Length is the number of objects, not number of bytes.
269 */
270 if (argc > 3)
271 length = simple_strtoul(argv[3], NULL, 16);
272 }
273
274 /*
275 * Print the lines.
276 *
277 * We buffer all read data, so we can make sure data is read only
278 * once.
279 */
280 nbytes = length;
281 do {
282 unsigned char linebuf[DISP_LINE_LEN];
283 unsigned char *cp;
284
285 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
286
287 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
288 puts ("Error reading the chip.\n");
289 else {
290 printf("%04x:", addr);
291 cp = linebuf;
292 for (j=0; j<linebytes; j++) {
293 printf(" %02x", *cp++);
294 addr++;
295 }
296 puts (" ");
297 cp = linebuf;
298 for (j=0; j<linebytes; j++) {
299 if ((*cp < 0x20) || (*cp > 0x7e))
300 puts (".");
301 else
302 printf("%c", *cp);
303 cp++;
304 }
305 putc ('\n');
306 }
307 nbytes -= linebytes;
308 } while (nbytes > 0);
309
310 i2c_dp_last_chip = chip;
311 i2c_dp_last_addr = addr;
312 i2c_dp_last_alen = alen;
313 i2c_dp_last_length = length;
314
315 return 0;
316 }
317
318
319 /* Write (fill) memory
320 *
321 * Syntax:
322 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
323 */
324 static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
325 {
326 uchar chip;
327 ulong addr;
328 uint alen;
329 uchar byte;
330 int count;
331
332 if ((argc < 4) || (argc > 5))
333 return cmd_usage(cmdtp);
334
335 /*
336 * Chip is always specified.
337 */
338 chip = simple_strtoul(argv[1], NULL, 16);
339
340 /*
341 * Address is always specified.
342 */
343 addr = simple_strtoul(argv[2], NULL, 16);
344 alen = get_alen(argv[2]);
345 if (alen > 3)
346 return cmd_usage(cmdtp);
347
348 /*
349 * Value to write is always specified.
350 */
351 byte = simple_strtoul(argv[3], NULL, 16);
352
353 /*
354 * Optional count
355 */
356 if (argc == 5)
357 count = simple_strtoul(argv[4], NULL, 16);
358 else
359 count = 1;
360
361 while (count-- > 0) {
362 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
363 puts ("Error writing the chip.\n");
364 /*
365 * Wait for the write to complete. The write can take
366 * up to 10mSec (we allow a little more time).
367 */
368 /*
369 * No write delay with FRAM devices.
370 */
371 #if !defined(CONFIG_SYS_I2C_FRAM)
372 udelay(11000);
373 #endif
374 }
375
376 return (0);
377 }
378
379 /* Calculate a CRC on memory
380 *
381 * Syntax:
382 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
383 */
384 static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
385 {
386 uchar chip;
387 ulong addr;
388 uint alen;
389 int count;
390 uchar byte;
391 ulong crc;
392 ulong err;
393
394 if (argc < 4)
395 return cmd_usage(cmdtp);
396
397 /*
398 * Chip is always specified.
399 */
400 chip = simple_strtoul(argv[1], NULL, 16);
401
402 /*
403 * Address is always specified.
404 */
405 addr = simple_strtoul(argv[2], NULL, 16);
406 alen = get_alen(argv[2]);
407 if (alen > 3)
408 return cmd_usage(cmdtp);
409
410 /*
411 * Count is always specified
412 */
413 count = simple_strtoul(argv[3], NULL, 16);
414
415 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
416 /*
417 * CRC a byte at a time. This is going to be slooow, but hey, the
418 * memories are small and slow too so hopefully nobody notices.
419 */
420 crc = 0;
421 err = 0;
422 while (count-- > 0) {
423 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
424 err++;
425 crc = crc32 (crc, &byte, 1);
426 addr++;
427 }
428 if (err > 0)
429 puts ("Error reading the chip,\n");
430 else
431 printf ("%08lx\n", crc);
432
433 return 0;
434 }
435
436 /* Modify memory.
437 *
438 * Syntax:
439 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
440 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
441 */
442
443 static int
444 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
445 {
446 uchar chip;
447 ulong addr;
448 uint alen;
449 ulong data;
450 int size = 1;
451 int nbytes;
452 extern char console_buffer[];
453
454 if (argc != 3)
455 return cmd_usage(cmdtp);
456
457 #ifdef CONFIG_BOOT_RETRY_TIME
458 reset_cmd_timeout(); /* got a good command to get here */
459 #endif
460 /*
461 * We use the last specified parameters, unless new ones are
462 * entered.
463 */
464 chip = i2c_mm_last_chip;
465 addr = i2c_mm_last_addr;
466 alen = i2c_mm_last_alen;
467
468 if ((flag & CMD_FLAG_REPEAT) == 0) {
469 /*
470 * New command specified. Check for a size specification.
471 * Defaults to byte if no or incorrect specification.
472 */
473 size = cmd_get_data_size(argv[0], 1);
474
475 /*
476 * Chip is always specified.
477 */
478 chip = simple_strtoul(argv[1], NULL, 16);
479
480 /*
481 * Address is always specified.
482 */
483 addr = simple_strtoul(argv[2], NULL, 16);
484 alen = get_alen(argv[2]);
485 if (alen > 3)
486 return cmd_usage(cmdtp);
487 }
488
489 /*
490 * Print the address, followed by value. Then accept input for
491 * the next value. A non-converted value exits.
492 */
493 do {
494 printf("%08lx:", addr);
495 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
496 puts ("\nError reading the chip,\n");
497 else {
498 data = cpu_to_be32(data);
499 if (size == 1)
500 printf(" %02lx", (data >> 24) & 0x000000FF);
501 else if (size == 2)
502 printf(" %04lx", (data >> 16) & 0x0000FFFF);
503 else
504 printf(" %08lx", data);
505 }
506
507 nbytes = readline (" ? ");
508 if (nbytes == 0) {
509 /*
510 * <CR> pressed as only input, don't modify current
511 * location and move to next.
512 */
513 if (incrflag)
514 addr += size;
515 nbytes = size;
516 #ifdef CONFIG_BOOT_RETRY_TIME
517 reset_cmd_timeout(); /* good enough to not time out */
518 #endif
519 }
520 #ifdef CONFIG_BOOT_RETRY_TIME
521 else if (nbytes == -2)
522 break; /* timed out, exit the command */
523 #endif
524 else {
525 char *endp;
526
527 data = simple_strtoul(console_buffer, &endp, 16);
528 if (size == 1)
529 data = data << 24;
530 else if (size == 2)
531 data = data << 16;
532 data = be32_to_cpu(data);
533 nbytes = endp - console_buffer;
534 if (nbytes) {
535 #ifdef CONFIG_BOOT_RETRY_TIME
536 /*
537 * good enough to not time out
538 */
539 reset_cmd_timeout();
540 #endif
541 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
542 puts ("Error writing the chip.\n");
543 #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
544 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
545 #endif
546 if (incrflag)
547 addr += size;
548 }
549 }
550 } while (nbytes);
551
552 i2c_mm_last_chip = chip;
553 i2c_mm_last_addr = addr;
554 i2c_mm_last_alen = alen;
555
556 return 0;
557 }
558
559 /*
560 * Syntax:
561 * i2c probe {addr}{.0, .1, .2}
562 */
563 static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
564 {
565 int j;
566 #if defined(CONFIG_SYS_I2C_NOPROBES)
567 int k, skip;
568 uchar bus = GET_BUS_NUM;
569 #endif /* NOPROBES */
570
571 puts ("Valid chip addresses:");
572 for (j = 0; j < 128; j++) {
573 #if defined(CONFIG_SYS_I2C_NOPROBES)
574 skip = 0;
575 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
576 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
577 skip = 1;
578 break;
579 }
580 }
581 if (skip)
582 continue;
583 #endif
584 if (i2c_probe(j) == 0)
585 printf(" %02X", j);
586 }
587 putc ('\n');
588
589 #if defined(CONFIG_SYS_I2C_NOPROBES)
590 puts ("Excluded chip addresses:");
591 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
592 if (COMPARE_BUS(bus,k))
593 printf(" %02X", NO_PROBE_ADDR(k));
594 }
595 putc ('\n');
596 #endif
597
598 return 0;
599 }
600
601 /*
602 * Syntax:
603 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
604 * {length} - Number of bytes to read
605 * {delay} - A DECIMAL number and defaults to 1000 uSec
606 */
607 static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
608 {
609 u_char chip;
610 ulong alen;
611 uint addr;
612 uint length;
613 u_char bytes[16];
614 int delay;
615
616 if (argc < 3)
617 return cmd_usage(cmdtp);
618
619 /*
620 * Chip is always specified.
621 */
622 chip = simple_strtoul(argv[1], NULL, 16);
623
624 /*
625 * Address is always specified.
626 */
627 addr = simple_strtoul(argv[2], NULL, 16);
628 alen = get_alen(argv[2]);
629 if (alen > 3)
630 return cmd_usage(cmdtp);
631
632 /*
633 * Length is the number of objects, not number of bytes.
634 */
635 length = 1;
636 length = simple_strtoul(argv[3], NULL, 16);
637 if (length > sizeof(bytes))
638 length = sizeof(bytes);
639
640 /*
641 * The delay time (uSec) is optional.
642 */
643 delay = 1000;
644 if (argc > 3)
645 delay = simple_strtoul(argv[4], NULL, 10);
646 /*
647 * Run the loop...
648 */
649 while (1) {
650 if (i2c_read(chip, addr, alen, bytes, length) != 0)
651 puts ("Error reading the chip.\n");
652 udelay(delay);
653 }
654
655 /* NOTREACHED */
656 return 0;
657 }
658
659 /*
660 * The SDRAM command is separately configured because many
661 * (most?) embedded boards don't use SDRAM DIMMs.
662 */
663 #if defined(CONFIG_CMD_SDRAM)
664 static void print_ddr2_tcyc (u_char const b)
665 {
666 printf ("%d.", (b >> 4) & 0x0F);
667 switch (b & 0x0F) {
668 case 0x0:
669 case 0x1:
670 case 0x2:
671 case 0x3:
672 case 0x4:
673 case 0x5:
674 case 0x6:
675 case 0x7:
676 case 0x8:
677 case 0x9:
678 printf ("%d ns\n", b & 0x0F);
679 break;
680 case 0xA:
681 puts ("25 ns\n");
682 break;
683 case 0xB:
684 puts ("33 ns\n");
685 break;
686 case 0xC:
687 puts ("66 ns\n");
688 break;
689 case 0xD:
690 puts ("75 ns\n");
691 break;
692 default:
693 puts ("?? ns\n");
694 break;
695 }
696 }
697
698 static void decode_bits (u_char const b, char const *str[], int const do_once)
699 {
700 u_char mask;
701
702 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
703 if (b & mask) {
704 puts (*str);
705 if (do_once)
706 return;
707 }
708 }
709 }
710
711 /*
712 * Syntax:
713 * i2c sdram {i2c_chip}
714 */
715 static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
716 {
717 enum { unknown, EDO, SDRAM, DDR2 } type;
718
719 u_char chip;
720 u_char data[128];
721 u_char cksum;
722 int j;
723
724 static const char *decode_CAS_DDR2[] = {
725 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
726 };
727
728 static const char *decode_CAS_default[] = {
729 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
730 };
731
732 static const char *decode_CS_WE_default[] = {
733 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
734 };
735
736 static const char *decode_byte21_default[] = {
737 " TBD (bit 7)\n",
738 " Redundant row address\n",
739 " Differential clock input\n",
740 " Registerd DQMB inputs\n",
741 " Buffered DQMB inputs\n",
742 " On-card PLL\n",
743 " Registered address/control lines\n",
744 " Buffered address/control lines\n"
745 };
746
747 static const char *decode_byte22_DDR2[] = {
748 " TBD (bit 7)\n",
749 " TBD (bit 6)\n",
750 " TBD (bit 5)\n",
751 " TBD (bit 4)\n",
752 " TBD (bit 3)\n",
753 " Supports partial array self refresh\n",
754 " Supports 50 ohm ODT\n",
755 " Supports weak driver\n"
756 };
757
758 static const char *decode_row_density_DDR2[] = {
759 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
760 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
761 };
762
763 static const char *decode_row_density_default[] = {
764 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
765 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
766 };
767
768 if (argc < 2)
769 return cmd_usage(cmdtp);
770
771 /*
772 * Chip is always specified.
773 */
774 chip = simple_strtoul (argv[1], NULL, 16);
775
776 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
777 puts ("No SDRAM Serial Presence Detect found.\n");
778 return 1;
779 }
780
781 cksum = 0;
782 for (j = 0; j < 63; j++) {
783 cksum += data[j];
784 }
785 if (cksum != data[63]) {
786 printf ("WARNING: Configuration data checksum failure:\n"
787 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
788 }
789 printf ("SPD data revision %d.%d\n",
790 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
791 printf ("Bytes used 0x%02X\n", data[0]);
792 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
793
794 puts ("Memory type ");
795 switch (data[2]) {
796 case 2:
797 type = EDO;
798 puts ("EDO\n");
799 break;
800 case 4:
801 type = SDRAM;
802 puts ("SDRAM\n");
803 break;
804 case 8:
805 type = DDR2;
806 puts ("DDR2\n");
807 break;
808 default:
809 type = unknown;
810 puts ("unknown\n");
811 break;
812 }
813
814 puts ("Row address bits ");
815 if ((data[3] & 0x00F0) == 0)
816 printf ("%d\n", data[3] & 0x0F);
817 else
818 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
819
820 puts ("Column address bits ");
821 if ((data[4] & 0x00F0) == 0)
822 printf ("%d\n", data[4] & 0x0F);
823 else
824 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
825
826 switch (type) {
827 case DDR2:
828 printf ("Number of ranks %d\n",
829 (data[5] & 0x07) + 1);
830 break;
831 default:
832 printf ("Module rows %d\n", data[5]);
833 break;
834 }
835
836 switch (type) {
837 case DDR2:
838 printf ("Module data width %d bits\n", data[6]);
839 break;
840 default:
841 printf ("Module data width %d bits\n",
842 (data[7] << 8) | data[6]);
843 break;
844 }
845
846 puts ("Interface signal levels ");
847 switch(data[8]) {
848 case 0: puts ("TTL 5.0 V\n"); break;
849 case 1: puts ("LVTTL\n"); break;
850 case 2: puts ("HSTL 1.5 V\n"); break;
851 case 3: puts ("SSTL 3.3 V\n"); break;
852 case 4: puts ("SSTL 2.5 V\n"); break;
853 case 5: puts ("SSTL 1.8 V\n"); break;
854 default: puts ("unknown\n"); break;
855 }
856
857 switch (type) {
858 case DDR2:
859 printf ("SDRAM cycle time ");
860 print_ddr2_tcyc (data[9]);
861 break;
862 default:
863 printf ("SDRAM cycle time %d.%d ns\n",
864 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
865 break;
866 }
867
868 switch (type) {
869 case DDR2:
870 printf ("SDRAM access time 0.%d%d ns\n",
871 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
872 break;
873 default:
874 printf ("SDRAM access time %d.%d ns\n",
875 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
876 break;
877 }
878
879 puts ("EDC configuration ");
880 switch (data[11]) {
881 case 0: puts ("None\n"); break;
882 case 1: puts ("Parity\n"); break;
883 case 2: puts ("ECC\n"); break;
884 default: puts ("unknown\n"); break;
885 }
886
887 if ((data[12] & 0x80) == 0)
888 puts ("No self refresh, rate ");
889 else
890 puts ("Self refresh, rate ");
891
892 switch(data[12] & 0x7F) {
893 case 0: puts ("15.625 us\n"); break;
894 case 1: puts ("3.9 us\n"); break;
895 case 2: puts ("7.8 us\n"); break;
896 case 3: puts ("31.3 us\n"); break;
897 case 4: puts ("62.5 us\n"); break;
898 case 5: puts ("125 us\n"); break;
899 default: puts ("unknown\n"); break;
900 }
901
902 switch (type) {
903 case DDR2:
904 printf ("SDRAM width (primary) %d\n", data[13]);
905 break;
906 default:
907 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
908 if ((data[13] & 0x80) != 0) {
909 printf (" (second bank) %d\n",
910 2 * (data[13] & 0x7F));
911 }
912 break;
913 }
914
915 switch (type) {
916 case DDR2:
917 if (data[14] != 0)
918 printf ("EDC width %d\n", data[14]);
919 break;
920 default:
921 if (data[14] != 0) {
922 printf ("EDC width %d\n",
923 data[14] & 0x7F);
924
925 if ((data[14] & 0x80) != 0) {
926 printf (" (second bank) %d\n",
927 2 * (data[14] & 0x7F));
928 }
929 }
930 break;
931 }
932
933 if (DDR2 != type) {
934 printf ("Min clock delay, back-to-back random column addresses "
935 "%d\n", data[15]);
936 }
937
938 puts ("Burst length(s) ");
939 if (data[16] & 0x80) puts (" Page");
940 if (data[16] & 0x08) puts (" 8");
941 if (data[16] & 0x04) puts (" 4");
942 if (data[16] & 0x02) puts (" 2");
943 if (data[16] & 0x01) puts (" 1");
944 putc ('\n');
945 printf ("Number of banks %d\n", data[17]);
946
947 switch (type) {
948 case DDR2:
949 puts ("CAS latency(s) ");
950 decode_bits (data[18], decode_CAS_DDR2, 0);
951 putc ('\n');
952 break;
953 default:
954 puts ("CAS latency(s) ");
955 decode_bits (data[18], decode_CAS_default, 0);
956 putc ('\n');
957 break;
958 }
959
960 if (DDR2 != type) {
961 puts ("CS latency(s) ");
962 decode_bits (data[19], decode_CS_WE_default, 0);
963 putc ('\n');
964 }
965
966 if (DDR2 != type) {
967 puts ("WE latency(s) ");
968 decode_bits (data[20], decode_CS_WE_default, 0);
969 putc ('\n');
970 }
971
972 switch (type) {
973 case DDR2:
974 puts ("Module attributes:\n");
975 if (data[21] & 0x80)
976 puts (" TBD (bit 7)\n");
977 if (data[21] & 0x40)
978 puts (" Analysis probe installed\n");
979 if (data[21] & 0x20)
980 puts (" TBD (bit 5)\n");
981 if (data[21] & 0x10)
982 puts (" FET switch external enable\n");
983 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
984 if (data[20] & 0x11) {
985 printf (" %d active registers on DIMM\n",
986 (data[21] & 0x03) + 1);
987 }
988 break;
989 default:
990 puts ("Module attributes:\n");
991 if (!data[21])
992 puts (" (none)\n");
993 else
994 decode_bits (data[21], decode_byte21_default, 0);
995 break;
996 }
997
998 switch (type) {
999 case DDR2:
1000 decode_bits (data[22], decode_byte22_DDR2, 0);
1001 break;
1002 default:
1003 puts ("Device attributes:\n");
1004 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1005 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1006 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1007 else puts (" Upper Vcc tolerance 10%\n");
1008 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1009 else puts (" Lower Vcc tolerance 10%\n");
1010 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1011 if (data[22] & 0x04) puts (" Supports precharge all\n");
1012 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1013 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1014 break;
1015 }
1016
1017 switch (type) {
1018 case DDR2:
1019 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1020 print_ddr2_tcyc (data[23]);
1021 break;
1022 default:
1023 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1024 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1025 break;
1026 }
1027
1028 switch (type) {
1029 case DDR2:
1030 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1031 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1032 break;
1033 default:
1034 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1035 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1036 break;
1037 }
1038
1039 switch (type) {
1040 case DDR2:
1041 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1042 print_ddr2_tcyc (data[25]);
1043 break;
1044 default:
1045 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1046 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1047 break;
1048 }
1049
1050 switch (type) {
1051 case DDR2:
1052 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1053 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1054 break;
1055 default:
1056 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1057 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1058 break;
1059 }
1060
1061 switch (type) {
1062 case DDR2:
1063 printf ("Minimum row precharge %d.%02d ns\n",
1064 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1065 break;
1066 default:
1067 printf ("Minimum row precharge %d ns\n", data[27]);
1068 break;
1069 }
1070
1071 switch (type) {
1072 case DDR2:
1073 printf ("Row active to row active min %d.%02d ns\n",
1074 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1075 break;
1076 default:
1077 printf ("Row active to row active min %d ns\n", data[28]);
1078 break;
1079 }
1080
1081 switch (type) {
1082 case DDR2:
1083 printf ("RAS to CAS delay min %d.%02d ns\n",
1084 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1085 break;
1086 default:
1087 printf ("RAS to CAS delay min %d ns\n", data[29]);
1088 break;
1089 }
1090
1091 printf ("Minimum RAS pulse width %d ns\n", data[30]);
1092
1093 switch (type) {
1094 case DDR2:
1095 puts ("Density of each row ");
1096 decode_bits (data[31], decode_row_density_DDR2, 1);
1097 putc ('\n');
1098 break;
1099 default:
1100 puts ("Density of each row ");
1101 decode_bits (data[31], decode_row_density_default, 1);
1102 putc ('\n');
1103 break;
1104 }
1105
1106 switch (type) {
1107 case DDR2:
1108 puts ("Command and Address setup ");
1109 if (data[32] >= 0xA0) {
1110 printf ("1.%d%d ns\n",
1111 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1112 } else {
1113 printf ("0.%d%d ns\n",
1114 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1115 }
1116 break;
1117 default:
1118 printf ("Command and Address setup %c%d.%d ns\n",
1119 (data[32] & 0x80) ? '-' : '+',
1120 (data[32] >> 4) & 0x07, data[32] & 0x0F);
1121 break;
1122 }
1123
1124 switch (type) {
1125 case DDR2:
1126 puts ("Command and Address hold ");
1127 if (data[33] >= 0xA0) {
1128 printf ("1.%d%d ns\n",
1129 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1130 } else {
1131 printf ("0.%d%d ns\n",
1132 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1133 }
1134 break;
1135 default:
1136 printf ("Command and Address hold %c%d.%d ns\n",
1137 (data[33] & 0x80) ? '-' : '+',
1138 (data[33] >> 4) & 0x07, data[33] & 0x0F);
1139 break;
1140 }
1141
1142 switch (type) {
1143 case DDR2:
1144 printf ("Data signal input setup 0.%d%d ns\n",
1145 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1146 break;
1147 default:
1148 printf ("Data signal input setup %c%d.%d ns\n",
1149 (data[34] & 0x80) ? '-' : '+',
1150 (data[34] >> 4) & 0x07, data[34] & 0x0F);
1151 break;
1152 }
1153
1154 switch (type) {
1155 case DDR2:
1156 printf ("Data signal input hold 0.%d%d ns\n",
1157 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1158 break;
1159 default:
1160 printf ("Data signal input hold %c%d.%d ns\n",
1161 (data[35] & 0x80) ? '-' : '+',
1162 (data[35] >> 4) & 0x07, data[35] & 0x0F);
1163 break;
1164 }
1165
1166 puts ("Manufacturer's JEDEC ID ");
1167 for (j = 64; j <= 71; j++)
1168 printf ("%02X ", data[j]);
1169 putc ('\n');
1170 printf ("Manufacturing Location %02X\n", data[72]);
1171 puts ("Manufacturer's Part Number ");
1172 for (j = 73; j <= 90; j++)
1173 printf ("%02X ", data[j]);
1174 putc ('\n');
1175 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1176 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1177 puts ("Assembly Serial Number ");
1178 for (j = 95; j <= 98; j++)
1179 printf ("%02X ", data[j]);
1180 putc ('\n');
1181
1182 if (DDR2 != type) {
1183 printf ("Speed rating PC%d\n",
1184 data[126] == 0x66 ? 66 : data[126]);
1185 }
1186 return 0;
1187 }
1188 #endif
1189
1190 #if defined(CONFIG_I2C_MUX)
1191 static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1192 {
1193 int ret=0;
1194
1195 if (argc == 1) {
1196 /* show all busses */
1197 I2C_MUX *mux;
1198 I2C_MUX_DEVICE *device = i2c_mux_devices;
1199
1200 printf ("Busses reached over muxes:\n");
1201 while (device != NULL) {
1202 printf ("Bus ID: %x\n", device->busid);
1203 printf (" reached over Mux(es):\n");
1204 mux = device->mux;
1205 while (mux != NULL) {
1206 printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
1207 mux = mux->next;
1208 }
1209 device = device->next;
1210 }
1211 } else {
1212 (void)i2c_mux_ident_muxstring ((uchar *)argv[1]);
1213 ret = 0;
1214 }
1215 return ret;
1216 }
1217 #endif /* CONFIG_I2C_MUX */
1218
1219 #if defined(CONFIG_I2C_MULTI_BUS)
1220 static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1221 {
1222 int bus_idx, ret=0;
1223
1224 if (argc == 1)
1225 /* querying current setting */
1226 printf("Current bus is %d\n", i2c_get_bus_num());
1227 else {
1228 bus_idx = simple_strtoul(argv[1], NULL, 10);
1229 printf("Setting bus to %d\n", bus_idx);
1230 ret = i2c_set_bus_num(bus_idx);
1231 if (ret)
1232 printf("Failure changing bus number (%d)\n", ret);
1233 }
1234 return ret;
1235 }
1236 #endif /* CONFIG_I2C_MULTI_BUS */
1237
1238 static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1239 {
1240 int speed, ret=0;
1241
1242 if (argc == 1)
1243 /* querying current speed */
1244 printf("Current bus speed=%d\n", i2c_get_bus_speed());
1245 else {
1246 speed = simple_strtoul(argv[1], NULL, 10);
1247 printf("Setting bus speed to %d Hz\n", speed);
1248 ret = i2c_set_bus_speed(speed);
1249 if (ret)
1250 printf("Failure changing bus speed (%d)\n", ret);
1251 }
1252 return ret;
1253 }
1254
1255 static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1256 {
1257 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1258 }
1259
1260 static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1261 {
1262 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1263 }
1264
1265 static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1266 {
1267 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1268 return 0;
1269 }
1270
1271 static cmd_tbl_t cmd_i2c_sub[] = {
1272 #if defined(CONFIG_I2C_MUX)
1273 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
1274 #endif /* CONFIG_I2C_MUX */
1275 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
1276 #if defined(CONFIG_I2C_MULTI_BUS)
1277 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
1278 #endif /* CONFIG_I2C_MULTI_BUS */
1279 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1280 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1281 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1282 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1283 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1284 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
1285 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
1286 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
1287 #if defined(CONFIG_CMD_SDRAM)
1288 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
1289 #endif
1290 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1291 };
1292
1293 #ifdef CONFIG_NEEDS_MANUAL_RELOC
1294 void i2c_reloc(void) {
1295 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1296 }
1297 #endif
1298
1299 static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1300 {
1301 cmd_tbl_t *c;
1302
1303 if (argc < 2)
1304 return cmd_usage(cmdtp);
1305
1306 /* Strip off leading 'i2c' command argument */
1307 argc--;
1308 argv++;
1309
1310 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1311
1312 if (c)
1313 return c->cmd(cmdtp, flag, argc, argv);
1314 else
1315 return cmd_usage(cmdtp);
1316 }
1317
1318 /***************************************************/
1319
1320 U_BOOT_CMD(
1321 i2c, 6, 1, do_i2c,
1322 "I2C sub-system",
1323 #if defined(CONFIG_I2C_MUX)
1324 "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
1325 #endif /* CONFIG_I2C_MUX */
1326 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
1327 #if defined(CONFIG_I2C_MULTI_BUS)
1328 "i2c dev [dev] - show or set current I2C bus\n"
1329 #endif /* CONFIG_I2C_MULTI_BUS */
1330 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
1331 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1332 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1333 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1334 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
1335 "i2c probe - show devices on the I2C bus\n"
1336 "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
1337 "i2c reset - re-init the I2C Controller\n"
1338 #if defined(CONFIG_CMD_SDRAM)
1339 "i2c sdram chip - print SDRAM configuration information\n"
1340 #endif
1341 "i2c speed [speed] - show or set I2C bus speed"
1342 );
1343
1344 #if defined(CONFIG_I2C_MUX)
1345 static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
1346 {
1347 I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
1348
1349 if (i2c_mux_devices == NULL) {
1350 i2c_mux_devices = dev;
1351 return 0;
1352 }
1353 while (devtmp->next != NULL)
1354 devtmp = devtmp->next;
1355
1356 devtmp->next = dev;
1357 return 0;
1358 }
1359
1360 I2C_MUX_DEVICE *i2c_mux_search_device(int id)
1361 {
1362 I2C_MUX_DEVICE *device = i2c_mux_devices;
1363
1364 while (device != NULL) {
1365 if (device->busid == id)
1366 return device;
1367 device = device->next;
1368 }
1369 return NULL;
1370 }
1371
1372 /* searches in the buf from *pos the next ':'.
1373 * returns:
1374 * 0 if found (with *pos = where)
1375 * < 0 if an error occured
1376 * > 0 if the end of buf is reached
1377 */
1378 static int i2c_mux_search_next (int *pos, uchar *buf, int len)
1379 {
1380 while ((buf[*pos] != ':') && (*pos < len)) {
1381 *pos += 1;
1382 }
1383 if (*pos >= len)
1384 return 1;
1385 if (buf[*pos] != ':')
1386 return -1;
1387 return 0;
1388 }
1389
1390 static int i2c_mux_get_busid (void)
1391 {
1392 int tmp = i2c_mux_busid;
1393
1394 i2c_mux_busid ++;
1395 return tmp;
1396 }
1397
1398 /* Analyses a Muxstring and immediately sends the
1399 commands to the muxes. Runs from flash.
1400 */
1401 int i2c_mux_ident_muxstring_f (uchar *buf)
1402 {
1403 int pos = 0;
1404 int oldpos;
1405 int ret = 0;
1406 int len = strlen((char *)buf);
1407 int chip;
1408 uchar channel;
1409 int was = 0;
1410
1411 while (ret == 0) {
1412 oldpos = pos;
1413 /* search name */
1414 ret = i2c_mux_search_next(&pos, buf, len);
1415 if (ret != 0)
1416 printf ("ERROR\n");
1417 /* search address */
1418 pos ++;
1419 oldpos = pos;
1420 ret = i2c_mux_search_next(&pos, buf, len);
1421 if (ret != 0)
1422 printf ("ERROR\n");
1423 buf[pos] = 0;
1424 chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1425 buf[pos] = ':';
1426 /* search channel */
1427 pos ++;
1428 oldpos = pos;
1429 ret = i2c_mux_search_next(&pos, buf, len);
1430 if (ret < 0)
1431 printf ("ERROR\n");
1432 was = 0;
1433 if (buf[pos] != 0) {
1434 buf[pos] = 0;
1435 was = 1;
1436 }
1437 channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1438 if (was)
1439 buf[pos] = ':';
1440 if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
1441 printf ("Error setting Mux: chip:%x channel: \
1442 %x\n", chip, channel);
1443 return -1;
1444 }
1445 pos ++;
1446 oldpos = pos;
1447
1448 }
1449
1450 return 0;
1451 }
1452
1453 /* Analyses a Muxstring and if this String is correct
1454 * adds a new I2C Bus.
1455 */
1456 I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
1457 {
1458 I2C_MUX_DEVICE *device;
1459 I2C_MUX *mux;
1460 int pos = 0;
1461 int oldpos;
1462 int ret = 0;
1463 int len = strlen((char *)buf);
1464 int was = 0;
1465
1466 device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
1467 device->mux = NULL;
1468 device->busid = i2c_mux_get_busid ();
1469 device->next = NULL;
1470 while (ret == 0) {
1471 mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
1472 mux->next = NULL;
1473 /* search name of mux */
1474 oldpos = pos;
1475 ret = i2c_mux_search_next(&pos, buf, len);
1476 if (ret != 0)
1477 printf ("%s no name.\n", __FUNCTION__);
1478 mux->name = (char *)malloc (pos - oldpos + 1);
1479 memcpy (mux->name, &buf[oldpos], pos - oldpos);
1480 mux->name[pos - oldpos] = 0;
1481 /* search address */
1482 pos ++;
1483 oldpos = pos;
1484 ret = i2c_mux_search_next(&pos, buf, len);
1485 if (ret != 0)
1486 printf ("%s no mux address.\n", __FUNCTION__);
1487 buf[pos] = 0;
1488 mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1489 buf[pos] = ':';
1490 /* search channel */
1491 pos ++;
1492 oldpos = pos;
1493 ret = i2c_mux_search_next(&pos, buf, len);
1494 if (ret < 0)
1495 printf ("%s no mux channel.\n", __FUNCTION__);
1496 was = 0;
1497 if (buf[pos] != 0) {
1498 buf[pos] = 0;
1499 was = 1;
1500 }
1501 mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1502 if (was)
1503 buf[pos] = ':';
1504 if (device->mux == NULL)
1505 device->mux = mux;
1506 else {
1507 I2C_MUX *muxtmp = device->mux;
1508 while (muxtmp->next != NULL) {
1509 muxtmp = muxtmp->next;
1510 }
1511 muxtmp->next = mux;
1512 }
1513 pos ++;
1514 oldpos = pos;
1515 }
1516 if (ret > 0) {
1517 /* Add Device */
1518 i2c_mux_add_device (device);
1519 return device;
1520 }
1521
1522 return NULL;
1523 }
1524
1525 int i2x_mux_select_mux(int bus)
1526 {
1527 I2C_MUX_DEVICE *dev;
1528 I2C_MUX *mux;
1529
1530 if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
1531 /* select Default Mux Bus */
1532 #if defined(CONFIG_SYS_I2C_IVM_BUS)
1533 i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
1534 #else
1535 {
1536 unsigned char *buf;
1537 buf = (unsigned char *) getenv("EEprom_ivm");
1538 if (buf != NULL)
1539 i2c_mux_ident_muxstring_f (buf);
1540 }
1541 #endif
1542 return 0;
1543 }
1544 dev = i2c_mux_search_device(bus);
1545 if (dev == NULL)
1546 return -1;
1547
1548 mux = dev->mux;
1549 while (mux != NULL) {
1550 /* do deblocking on each level of mux, before mux config */
1551 i2c_init_board();
1552 if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
1553 printf ("Error setting Mux: chip:%x channel: \
1554 %x\n", mux->chip, mux->channel);
1555 return -1;
1556 }
1557 mux = mux->next;
1558 }
1559 /* do deblocking on each level of mux and after mux config */
1560 i2c_init_board();
1561 return 0;
1562 }
1563 #endif /* CONFIG_I2C_MUX */