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1 /*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * I2C Functions similar to the standard memory functions.
26 *
27 * There are several parameters in many of the commands that bear further
28 * explanations:
29 *
30 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
31 * Each I2C chip on the bus has a unique address. On the I2C data bus,
32 * the address is the upper seven bits and the LSB is the "read/write"
33 * bit. Note that the {i2c_chip} address specified on the command
34 * line is not shifted up: e.g. a typical EEPROM memory chip may have
35 * an I2C address of 0x50, but the data put on the bus will be 0xA0
36 * for write and 0xA1 for read. This "non shifted" address notation
37 * matches at least half of the data sheets :-/.
38 *
39 * {addr} is the address (or offset) within the chip. Small memory
40 * chips have 8 bit addresses. Large memory chips have 16 bit
41 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
42 * Many non-memory chips have multiple registers and {addr} is used
43 * as the register index. Some non-memory chips have only one register
44 * and therefore don't need any {addr} parameter.
45 *
46 * The default {addr} parameter is one byte (.1) which works well for
47 * memories and registers with 8 bits of address space.
48 *
49 * You can specify the length of the {addr} field with the optional .0,
50 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
51 * manipulating a single register device which doesn't use an address
52 * field, use "0.0" for the address and the ".0" length field will
53 * suppress the address in the I2C data stream. This also works for
54 * successive reads using the I2C auto-incrementing memory pointer.
55 *
56 * If you are manipulating a large memory with 2-byte addresses, use
57 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
58 *
59 * Then there are the unfortunate memory chips that spill the most
60 * significant 1, 2, or 3 bits of address into the chip address byte.
61 * This effectively makes one chip (logically) look like 2, 4, or
62 * 8 chips. This is handled (awkwardly) by #defining
63 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
64 * {addr} field (since .1 is the default, it doesn't actually have to
65 * be specified). Examples: given a memory chip at I2C chip address
66 * 0x50, the following would happen...
67 * i2c md 50 0 10 display 16 bytes starting at 0x000
68 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
69 * i2c md 50 100 10 display 16 bytes starting at 0x100
70 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
71 * i2c md 50 210 10 display 16 bytes starting at 0x210
72 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
73 * This is awfully ugly. It would be nice if someone would think up
74 * a better way of handling this.
75 *
76 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
77 */
78
79 #include <common.h>
80 #include <command.h>
81 #include <environment.h>
82 #include <i2c.h>
83 #include <malloc.h>
84 #include <asm/byteorder.h>
85
86 /* Display values from last command.
87 * Memory modify remembered values are different from display memory.
88 */
89 static uchar i2c_dp_last_chip;
90 static uint i2c_dp_last_addr;
91 static uint i2c_dp_last_alen;
92 static uint i2c_dp_last_length = 0x10;
93
94 static uchar i2c_mm_last_chip;
95 static uint i2c_mm_last_addr;
96 static uint i2c_mm_last_alen;
97
98 /* If only one I2C bus is present, the list of devices to ignore when
99 * the probe command is issued is represented by a 1D array of addresses.
100 * When multiple buses are present, the list is an array of bus-address
101 * pairs. The following macros take care of this */
102
103 #if defined(CONFIG_SYS_I2C_NOPROBES)
104 #if defined(CONFIG_I2C_MULTI_BUS)
105 static struct
106 {
107 uchar bus;
108 uchar addr;
109 } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
110 #define GET_BUS_NUM i2c_get_bus_num()
111 #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
112 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
113 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
114 #else /* single bus */
115 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
116 #define GET_BUS_NUM 0
117 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
118 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
119 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
120 #endif /* CONFIG_MULTI_BUS */
121
122 #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
123 #endif
124
125 #if defined(CONFIG_I2C_MUX)
126 static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
127 static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
128
129 DECLARE_GLOBAL_DATA_PTR;
130
131 #endif
132
133 #define DISP_LINE_LEN 16
134
135 /* implement possible board specific board init */
136 void __def_i2c_init_board(void)
137 {
138 return;
139 }
140 void i2c_init_board(void)
141 __attribute__((weak, alias("__def_i2c_init_board")));
142
143 /* TODO: Implement architecture-specific get/set functions */
144 unsigned int __def_i2c_get_bus_speed(void)
145 {
146 return CONFIG_SYS_I2C_SPEED;
147 }
148 unsigned int i2c_get_bus_speed(void)
149 __attribute__((weak, alias("__def_i2c_get_bus_speed")));
150
151 int __def_i2c_set_bus_speed(unsigned int speed)
152 {
153 if (speed != CONFIG_SYS_I2C_SPEED)
154 return -1;
155
156 return 0;
157 }
158 int i2c_set_bus_speed(unsigned int)
159 __attribute__((weak, alias("__def_i2c_set_bus_speed")));
160
161 /*
162 * get_alen: small parser helper function to get address length
163 * returns the address length
164 */
165 static uint get_alen(char *arg)
166 {
167 int j;
168 int alen;
169
170 alen = 1;
171 for (j = 0; j < 8; j++) {
172 if (arg[j] == '.') {
173 alen = arg[j+1] - '0';
174 break;
175 } else if (arg[j] == '\0')
176 break;
177 }
178 return alen;
179 }
180
181 /*
182 * Syntax:
183 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
184 */
185
186 static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
187 {
188 u_char chip;
189 uint devaddr, alen, length;
190 u_char *memaddr;
191
192 if (argc != 5)
193 return cmd_usage(cmdtp);
194
195 /*
196 * I2C chip address
197 */
198 chip = simple_strtoul(argv[1], NULL, 16);
199
200 /*
201 * I2C data address within the chip. This can be 1 or
202 * 2 bytes long. Some day it might be 3 bytes long :-).
203 */
204 devaddr = simple_strtoul(argv[2], NULL, 16);
205 alen = get_alen(argv[2]);
206 if (alen > 3)
207 return cmd_usage(cmdtp);
208
209 /*
210 * Length is the number of objects, not number of bytes.
211 */
212 length = simple_strtoul(argv[3], NULL, 16);
213
214 /*
215 * memaddr is the address where to store things in memory
216 */
217 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
218
219 if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
220 puts ("Error reading the chip.\n");
221 return 1;
222 }
223 return 0;
224 }
225
226 /*
227 * Syntax:
228 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
229 */
230 static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
231 {
232 u_char chip;
233 uint addr, alen, length;
234 int j, nbytes, linebytes;
235
236 /* We use the last specified parameters, unless new ones are
237 * entered.
238 */
239 chip = i2c_dp_last_chip;
240 addr = i2c_dp_last_addr;
241 alen = i2c_dp_last_alen;
242 length = i2c_dp_last_length;
243
244 if (argc < 3)
245 return cmd_usage(cmdtp);
246
247 if ((flag & CMD_FLAG_REPEAT) == 0) {
248 /*
249 * New command specified.
250 */
251
252 /*
253 * I2C chip address
254 */
255 chip = simple_strtoul(argv[1], NULL, 16);
256
257 /*
258 * I2C data address within the chip. This can be 1 or
259 * 2 bytes long. Some day it might be 3 bytes long :-).
260 */
261 addr = simple_strtoul(argv[2], NULL, 16);
262 alen = get_alen(argv[2]);
263 if (alen > 3)
264 return cmd_usage(cmdtp);
265
266 /*
267 * If another parameter, it is the length to display.
268 * Length is the number of objects, not number of bytes.
269 */
270 if (argc > 3)
271 length = simple_strtoul(argv[3], NULL, 16);
272 }
273
274 /*
275 * Print the lines.
276 *
277 * We buffer all read data, so we can make sure data is read only
278 * once.
279 */
280 nbytes = length;
281 do {
282 unsigned char linebuf[DISP_LINE_LEN];
283 unsigned char *cp;
284
285 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
286
287 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
288 puts ("Error reading the chip.\n");
289 else {
290 printf("%04x:", addr);
291 cp = linebuf;
292 for (j=0; j<linebytes; j++) {
293 printf(" %02x", *cp++);
294 addr++;
295 }
296 puts (" ");
297 cp = linebuf;
298 for (j=0; j<linebytes; j++) {
299 if ((*cp < 0x20) || (*cp > 0x7e))
300 puts (".");
301 else
302 printf("%c", *cp);
303 cp++;
304 }
305 putc ('\n');
306 }
307 nbytes -= linebytes;
308 } while (nbytes > 0);
309
310 i2c_dp_last_chip = chip;
311 i2c_dp_last_addr = addr;
312 i2c_dp_last_alen = alen;
313 i2c_dp_last_length = length;
314
315 return 0;
316 }
317
318
319 /* Write (fill) memory
320 *
321 * Syntax:
322 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
323 */
324 static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
325 {
326 uchar chip;
327 ulong addr;
328 uint alen;
329 uchar byte;
330 int count;
331
332 if ((argc < 4) || (argc > 5))
333 return cmd_usage(cmdtp);
334
335 /*
336 * Chip is always specified.
337 */
338 chip = simple_strtoul(argv[1], NULL, 16);
339
340 /*
341 * Address is always specified.
342 */
343 addr = simple_strtoul(argv[2], NULL, 16);
344 alen = get_alen(argv[2]);
345 if (alen > 3)
346 return cmd_usage(cmdtp);
347
348 /*
349 * Value to write is always specified.
350 */
351 byte = simple_strtoul(argv[3], NULL, 16);
352
353 /*
354 * Optional count
355 */
356 if (argc == 5)
357 count = simple_strtoul(argv[4], NULL, 16);
358 else
359 count = 1;
360
361 while (count-- > 0) {
362 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
363 puts ("Error writing the chip.\n");
364 /*
365 * Wait for the write to complete. The write can take
366 * up to 10mSec (we allow a little more time).
367 */
368 /*
369 * No write delay with FRAM devices.
370 */
371 #if !defined(CONFIG_SYS_I2C_FRAM)
372 udelay(11000);
373 #endif
374 }
375
376 return (0);
377 }
378
379 /* Calculate a CRC on memory
380 *
381 * Syntax:
382 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
383 */
384 static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
385 {
386 uchar chip;
387 ulong addr;
388 uint alen;
389 int count;
390 uchar byte;
391 ulong crc;
392 ulong err;
393
394 if (argc < 4)
395 return cmd_usage(cmdtp);
396
397 /*
398 * Chip is always specified.
399 */
400 chip = simple_strtoul(argv[1], NULL, 16);
401
402 /*
403 * Address is always specified.
404 */
405 addr = simple_strtoul(argv[2], NULL, 16);
406 alen = get_alen(argv[2]);
407 if (alen > 3)
408 return cmd_usage(cmdtp);
409
410 /*
411 * Count is always specified
412 */
413 count = simple_strtoul(argv[3], NULL, 16);
414
415 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
416 /*
417 * CRC a byte at a time. This is going to be slooow, but hey, the
418 * memories are small and slow too so hopefully nobody notices.
419 */
420 crc = 0;
421 err = 0;
422 while (count-- > 0) {
423 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
424 err++;
425 crc = crc32 (crc, &byte, 1);
426 addr++;
427 }
428 if (err > 0)
429 puts ("Error reading the chip,\n");
430 else
431 printf ("%08lx\n", crc);
432
433 return 0;
434 }
435
436 /* Modify memory.
437 *
438 * Syntax:
439 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
440 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
441 */
442
443 static int
444 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
445 {
446 uchar chip;
447 ulong addr;
448 uint alen;
449 ulong data;
450 int size = 1;
451 int nbytes;
452
453 if (argc != 3)
454 return cmd_usage(cmdtp);
455
456 #ifdef CONFIG_BOOT_RETRY_TIME
457 reset_cmd_timeout(); /* got a good command to get here */
458 #endif
459 /*
460 * We use the last specified parameters, unless new ones are
461 * entered.
462 */
463 chip = i2c_mm_last_chip;
464 addr = i2c_mm_last_addr;
465 alen = i2c_mm_last_alen;
466
467 if ((flag & CMD_FLAG_REPEAT) == 0) {
468 /*
469 * New command specified. Check for a size specification.
470 * Defaults to byte if no or incorrect specification.
471 */
472 size = cmd_get_data_size(argv[0], 1);
473
474 /*
475 * Chip is always specified.
476 */
477 chip = simple_strtoul(argv[1], NULL, 16);
478
479 /*
480 * Address is always specified.
481 */
482 addr = simple_strtoul(argv[2], NULL, 16);
483 alen = get_alen(argv[2]);
484 if (alen > 3)
485 return cmd_usage(cmdtp);
486 }
487
488 /*
489 * Print the address, followed by value. Then accept input for
490 * the next value. A non-converted value exits.
491 */
492 do {
493 printf("%08lx:", addr);
494 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
495 puts ("\nError reading the chip,\n");
496 else {
497 data = cpu_to_be32(data);
498 if (size == 1)
499 printf(" %02lx", (data >> 24) & 0x000000FF);
500 else if (size == 2)
501 printf(" %04lx", (data >> 16) & 0x0000FFFF);
502 else
503 printf(" %08lx", data);
504 }
505
506 nbytes = readline (" ? ");
507 if (nbytes == 0) {
508 /*
509 * <CR> pressed as only input, don't modify current
510 * location and move to next.
511 */
512 if (incrflag)
513 addr += size;
514 nbytes = size;
515 #ifdef CONFIG_BOOT_RETRY_TIME
516 reset_cmd_timeout(); /* good enough to not time out */
517 #endif
518 }
519 #ifdef CONFIG_BOOT_RETRY_TIME
520 else if (nbytes == -2)
521 break; /* timed out, exit the command */
522 #endif
523 else {
524 char *endp;
525
526 data = simple_strtoul(console_buffer, &endp, 16);
527 if (size == 1)
528 data = data << 24;
529 else if (size == 2)
530 data = data << 16;
531 data = be32_to_cpu(data);
532 nbytes = endp - console_buffer;
533 if (nbytes) {
534 #ifdef CONFIG_BOOT_RETRY_TIME
535 /*
536 * good enough to not time out
537 */
538 reset_cmd_timeout();
539 #endif
540 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
541 puts ("Error writing the chip.\n");
542 #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
543 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
544 #endif
545 if (incrflag)
546 addr += size;
547 }
548 }
549 } while (nbytes);
550
551 i2c_mm_last_chip = chip;
552 i2c_mm_last_addr = addr;
553 i2c_mm_last_alen = alen;
554
555 return 0;
556 }
557
558 /*
559 * Syntax:
560 * i2c probe {addr}{.0, .1, .2}
561 */
562 static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
563 {
564 int j;
565 #if defined(CONFIG_SYS_I2C_NOPROBES)
566 int k, skip;
567 uchar bus = GET_BUS_NUM;
568 #endif /* NOPROBES */
569
570 puts ("Valid chip addresses:");
571 for (j = 0; j < 128; j++) {
572 #if defined(CONFIG_SYS_I2C_NOPROBES)
573 skip = 0;
574 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
575 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
576 skip = 1;
577 break;
578 }
579 }
580 if (skip)
581 continue;
582 #endif
583 if (i2c_probe(j) == 0)
584 printf(" %02X", j);
585 }
586 putc ('\n');
587
588 #if defined(CONFIG_SYS_I2C_NOPROBES)
589 puts ("Excluded chip addresses:");
590 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
591 if (COMPARE_BUS(bus,k))
592 printf(" %02X", NO_PROBE_ADDR(k));
593 }
594 putc ('\n');
595 #endif
596
597 return 0;
598 }
599
600 /*
601 * Syntax:
602 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
603 * {length} - Number of bytes to read
604 * {delay} - A DECIMAL number and defaults to 1000 uSec
605 */
606 static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
607 {
608 u_char chip;
609 ulong alen;
610 uint addr;
611 uint length;
612 u_char bytes[16];
613 int delay;
614
615 if (argc < 3)
616 return cmd_usage(cmdtp);
617
618 /*
619 * Chip is always specified.
620 */
621 chip = simple_strtoul(argv[1], NULL, 16);
622
623 /*
624 * Address is always specified.
625 */
626 addr = simple_strtoul(argv[2], NULL, 16);
627 alen = get_alen(argv[2]);
628 if (alen > 3)
629 return cmd_usage(cmdtp);
630
631 /*
632 * Length is the number of objects, not number of bytes.
633 */
634 length = 1;
635 length = simple_strtoul(argv[3], NULL, 16);
636 if (length > sizeof(bytes))
637 length = sizeof(bytes);
638
639 /*
640 * The delay time (uSec) is optional.
641 */
642 delay = 1000;
643 if (argc > 3)
644 delay = simple_strtoul(argv[4], NULL, 10);
645 /*
646 * Run the loop...
647 */
648 while (1) {
649 if (i2c_read(chip, addr, alen, bytes, length) != 0)
650 puts ("Error reading the chip.\n");
651 udelay(delay);
652 }
653
654 /* NOTREACHED */
655 return 0;
656 }
657
658 /*
659 * The SDRAM command is separately configured because many
660 * (most?) embedded boards don't use SDRAM DIMMs.
661 */
662 #if defined(CONFIG_CMD_SDRAM)
663 static void print_ddr2_tcyc (u_char const b)
664 {
665 printf ("%d.", (b >> 4) & 0x0F);
666 switch (b & 0x0F) {
667 case 0x0:
668 case 0x1:
669 case 0x2:
670 case 0x3:
671 case 0x4:
672 case 0x5:
673 case 0x6:
674 case 0x7:
675 case 0x8:
676 case 0x9:
677 printf ("%d ns\n", b & 0x0F);
678 break;
679 case 0xA:
680 puts ("25 ns\n");
681 break;
682 case 0xB:
683 puts ("33 ns\n");
684 break;
685 case 0xC:
686 puts ("66 ns\n");
687 break;
688 case 0xD:
689 puts ("75 ns\n");
690 break;
691 default:
692 puts ("?? ns\n");
693 break;
694 }
695 }
696
697 static void decode_bits (u_char const b, char const *str[], int const do_once)
698 {
699 u_char mask;
700
701 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
702 if (b & mask) {
703 puts (*str);
704 if (do_once)
705 return;
706 }
707 }
708 }
709
710 /*
711 * Syntax:
712 * i2c sdram {i2c_chip}
713 */
714 static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
715 {
716 enum { unknown, EDO, SDRAM, DDR2 } type;
717
718 u_char chip;
719 u_char data[128];
720 u_char cksum;
721 int j;
722
723 static const char *decode_CAS_DDR2[] = {
724 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
725 };
726
727 static const char *decode_CAS_default[] = {
728 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
729 };
730
731 static const char *decode_CS_WE_default[] = {
732 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
733 };
734
735 static const char *decode_byte21_default[] = {
736 " TBD (bit 7)\n",
737 " Redundant row address\n",
738 " Differential clock input\n",
739 " Registerd DQMB inputs\n",
740 " Buffered DQMB inputs\n",
741 " On-card PLL\n",
742 " Registered address/control lines\n",
743 " Buffered address/control lines\n"
744 };
745
746 static const char *decode_byte22_DDR2[] = {
747 " TBD (bit 7)\n",
748 " TBD (bit 6)\n",
749 " TBD (bit 5)\n",
750 " TBD (bit 4)\n",
751 " TBD (bit 3)\n",
752 " Supports partial array self refresh\n",
753 " Supports 50 ohm ODT\n",
754 " Supports weak driver\n"
755 };
756
757 static const char *decode_row_density_DDR2[] = {
758 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
759 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
760 };
761
762 static const char *decode_row_density_default[] = {
763 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
764 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
765 };
766
767 if (argc < 2)
768 return cmd_usage(cmdtp);
769
770 /*
771 * Chip is always specified.
772 */
773 chip = simple_strtoul (argv[1], NULL, 16);
774
775 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
776 puts ("No SDRAM Serial Presence Detect found.\n");
777 return 1;
778 }
779
780 cksum = 0;
781 for (j = 0; j < 63; j++) {
782 cksum += data[j];
783 }
784 if (cksum != data[63]) {
785 printf ("WARNING: Configuration data checksum failure:\n"
786 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
787 }
788 printf ("SPD data revision %d.%d\n",
789 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
790 printf ("Bytes used 0x%02X\n", data[0]);
791 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
792
793 puts ("Memory type ");
794 switch (data[2]) {
795 case 2:
796 type = EDO;
797 puts ("EDO\n");
798 break;
799 case 4:
800 type = SDRAM;
801 puts ("SDRAM\n");
802 break;
803 case 8:
804 type = DDR2;
805 puts ("DDR2\n");
806 break;
807 default:
808 type = unknown;
809 puts ("unknown\n");
810 break;
811 }
812
813 puts ("Row address bits ");
814 if ((data[3] & 0x00F0) == 0)
815 printf ("%d\n", data[3] & 0x0F);
816 else
817 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
818
819 puts ("Column address bits ");
820 if ((data[4] & 0x00F0) == 0)
821 printf ("%d\n", data[4] & 0x0F);
822 else
823 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
824
825 switch (type) {
826 case DDR2:
827 printf ("Number of ranks %d\n",
828 (data[5] & 0x07) + 1);
829 break;
830 default:
831 printf ("Module rows %d\n", data[5]);
832 break;
833 }
834
835 switch (type) {
836 case DDR2:
837 printf ("Module data width %d bits\n", data[6]);
838 break;
839 default:
840 printf ("Module data width %d bits\n",
841 (data[7] << 8) | data[6]);
842 break;
843 }
844
845 puts ("Interface signal levels ");
846 switch(data[8]) {
847 case 0: puts ("TTL 5.0 V\n"); break;
848 case 1: puts ("LVTTL\n"); break;
849 case 2: puts ("HSTL 1.5 V\n"); break;
850 case 3: puts ("SSTL 3.3 V\n"); break;
851 case 4: puts ("SSTL 2.5 V\n"); break;
852 case 5: puts ("SSTL 1.8 V\n"); break;
853 default: puts ("unknown\n"); break;
854 }
855
856 switch (type) {
857 case DDR2:
858 printf ("SDRAM cycle time ");
859 print_ddr2_tcyc (data[9]);
860 break;
861 default:
862 printf ("SDRAM cycle time %d.%d ns\n",
863 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
864 break;
865 }
866
867 switch (type) {
868 case DDR2:
869 printf ("SDRAM access time 0.%d%d ns\n",
870 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
871 break;
872 default:
873 printf ("SDRAM access time %d.%d ns\n",
874 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
875 break;
876 }
877
878 puts ("EDC configuration ");
879 switch (data[11]) {
880 case 0: puts ("None\n"); break;
881 case 1: puts ("Parity\n"); break;
882 case 2: puts ("ECC\n"); break;
883 default: puts ("unknown\n"); break;
884 }
885
886 if ((data[12] & 0x80) == 0)
887 puts ("No self refresh, rate ");
888 else
889 puts ("Self refresh, rate ");
890
891 switch(data[12] & 0x7F) {
892 case 0: puts ("15.625 us\n"); break;
893 case 1: puts ("3.9 us\n"); break;
894 case 2: puts ("7.8 us\n"); break;
895 case 3: puts ("31.3 us\n"); break;
896 case 4: puts ("62.5 us\n"); break;
897 case 5: puts ("125 us\n"); break;
898 default: puts ("unknown\n"); break;
899 }
900
901 switch (type) {
902 case DDR2:
903 printf ("SDRAM width (primary) %d\n", data[13]);
904 break;
905 default:
906 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
907 if ((data[13] & 0x80) != 0) {
908 printf (" (second bank) %d\n",
909 2 * (data[13] & 0x7F));
910 }
911 break;
912 }
913
914 switch (type) {
915 case DDR2:
916 if (data[14] != 0)
917 printf ("EDC width %d\n", data[14]);
918 break;
919 default:
920 if (data[14] != 0) {
921 printf ("EDC width %d\n",
922 data[14] & 0x7F);
923
924 if ((data[14] & 0x80) != 0) {
925 printf (" (second bank) %d\n",
926 2 * (data[14] & 0x7F));
927 }
928 }
929 break;
930 }
931
932 if (DDR2 != type) {
933 printf ("Min clock delay, back-to-back random column addresses "
934 "%d\n", data[15]);
935 }
936
937 puts ("Burst length(s) ");
938 if (data[16] & 0x80) puts (" Page");
939 if (data[16] & 0x08) puts (" 8");
940 if (data[16] & 0x04) puts (" 4");
941 if (data[16] & 0x02) puts (" 2");
942 if (data[16] & 0x01) puts (" 1");
943 putc ('\n');
944 printf ("Number of banks %d\n", data[17]);
945
946 switch (type) {
947 case DDR2:
948 puts ("CAS latency(s) ");
949 decode_bits (data[18], decode_CAS_DDR2, 0);
950 putc ('\n');
951 break;
952 default:
953 puts ("CAS latency(s) ");
954 decode_bits (data[18], decode_CAS_default, 0);
955 putc ('\n');
956 break;
957 }
958
959 if (DDR2 != type) {
960 puts ("CS latency(s) ");
961 decode_bits (data[19], decode_CS_WE_default, 0);
962 putc ('\n');
963 }
964
965 if (DDR2 != type) {
966 puts ("WE latency(s) ");
967 decode_bits (data[20], decode_CS_WE_default, 0);
968 putc ('\n');
969 }
970
971 switch (type) {
972 case DDR2:
973 puts ("Module attributes:\n");
974 if (data[21] & 0x80)
975 puts (" TBD (bit 7)\n");
976 if (data[21] & 0x40)
977 puts (" Analysis probe installed\n");
978 if (data[21] & 0x20)
979 puts (" TBD (bit 5)\n");
980 if (data[21] & 0x10)
981 puts (" FET switch external enable\n");
982 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
983 if (data[20] & 0x11) {
984 printf (" %d active registers on DIMM\n",
985 (data[21] & 0x03) + 1);
986 }
987 break;
988 default:
989 puts ("Module attributes:\n");
990 if (!data[21])
991 puts (" (none)\n");
992 else
993 decode_bits (data[21], decode_byte21_default, 0);
994 break;
995 }
996
997 switch (type) {
998 case DDR2:
999 decode_bits (data[22], decode_byte22_DDR2, 0);
1000 break;
1001 default:
1002 puts ("Device attributes:\n");
1003 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1004 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1005 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1006 else puts (" Upper Vcc tolerance 10%\n");
1007 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1008 else puts (" Lower Vcc tolerance 10%\n");
1009 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1010 if (data[22] & 0x04) puts (" Supports precharge all\n");
1011 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1012 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1013 break;
1014 }
1015
1016 switch (type) {
1017 case DDR2:
1018 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1019 print_ddr2_tcyc (data[23]);
1020 break;
1021 default:
1022 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1023 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1024 break;
1025 }
1026
1027 switch (type) {
1028 case DDR2:
1029 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1030 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1031 break;
1032 default:
1033 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1034 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1035 break;
1036 }
1037
1038 switch (type) {
1039 case DDR2:
1040 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1041 print_ddr2_tcyc (data[25]);
1042 break;
1043 default:
1044 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1045 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1046 break;
1047 }
1048
1049 switch (type) {
1050 case DDR2:
1051 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1052 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1053 break;
1054 default:
1055 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1056 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1057 break;
1058 }
1059
1060 switch (type) {
1061 case DDR2:
1062 printf ("Minimum row precharge %d.%02d ns\n",
1063 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1064 break;
1065 default:
1066 printf ("Minimum row precharge %d ns\n", data[27]);
1067 break;
1068 }
1069
1070 switch (type) {
1071 case DDR2:
1072 printf ("Row active to row active min %d.%02d ns\n",
1073 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1074 break;
1075 default:
1076 printf ("Row active to row active min %d ns\n", data[28]);
1077 break;
1078 }
1079
1080 switch (type) {
1081 case DDR2:
1082 printf ("RAS to CAS delay min %d.%02d ns\n",
1083 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1084 break;
1085 default:
1086 printf ("RAS to CAS delay min %d ns\n", data[29]);
1087 break;
1088 }
1089
1090 printf ("Minimum RAS pulse width %d ns\n", data[30]);
1091
1092 switch (type) {
1093 case DDR2:
1094 puts ("Density of each row ");
1095 decode_bits (data[31], decode_row_density_DDR2, 1);
1096 putc ('\n');
1097 break;
1098 default:
1099 puts ("Density of each row ");
1100 decode_bits (data[31], decode_row_density_default, 1);
1101 putc ('\n');
1102 break;
1103 }
1104
1105 switch (type) {
1106 case DDR2:
1107 puts ("Command and Address setup ");
1108 if (data[32] >= 0xA0) {
1109 printf ("1.%d%d ns\n",
1110 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1111 } else {
1112 printf ("0.%d%d ns\n",
1113 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1114 }
1115 break;
1116 default:
1117 printf ("Command and Address setup %c%d.%d ns\n",
1118 (data[32] & 0x80) ? '-' : '+',
1119 (data[32] >> 4) & 0x07, data[32] & 0x0F);
1120 break;
1121 }
1122
1123 switch (type) {
1124 case DDR2:
1125 puts ("Command and Address hold ");
1126 if (data[33] >= 0xA0) {
1127 printf ("1.%d%d ns\n",
1128 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1129 } else {
1130 printf ("0.%d%d ns\n",
1131 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1132 }
1133 break;
1134 default:
1135 printf ("Command and Address hold %c%d.%d ns\n",
1136 (data[33] & 0x80) ? '-' : '+',
1137 (data[33] >> 4) & 0x07, data[33] & 0x0F);
1138 break;
1139 }
1140
1141 switch (type) {
1142 case DDR2:
1143 printf ("Data signal input setup 0.%d%d ns\n",
1144 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1145 break;
1146 default:
1147 printf ("Data signal input setup %c%d.%d ns\n",
1148 (data[34] & 0x80) ? '-' : '+',
1149 (data[34] >> 4) & 0x07, data[34] & 0x0F);
1150 break;
1151 }
1152
1153 switch (type) {
1154 case DDR2:
1155 printf ("Data signal input hold 0.%d%d ns\n",
1156 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1157 break;
1158 default:
1159 printf ("Data signal input hold %c%d.%d ns\n",
1160 (data[35] & 0x80) ? '-' : '+',
1161 (data[35] >> 4) & 0x07, data[35] & 0x0F);
1162 break;
1163 }
1164
1165 puts ("Manufacturer's JEDEC ID ");
1166 for (j = 64; j <= 71; j++)
1167 printf ("%02X ", data[j]);
1168 putc ('\n');
1169 printf ("Manufacturing Location %02X\n", data[72]);
1170 puts ("Manufacturer's Part Number ");
1171 for (j = 73; j <= 90; j++)
1172 printf ("%02X ", data[j]);
1173 putc ('\n');
1174 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1175 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1176 puts ("Assembly Serial Number ");
1177 for (j = 95; j <= 98; j++)
1178 printf ("%02X ", data[j]);
1179 putc ('\n');
1180
1181 if (DDR2 != type) {
1182 printf ("Speed rating PC%d\n",
1183 data[126] == 0x66 ? 66 : data[126]);
1184 }
1185 return 0;
1186 }
1187 #endif
1188
1189 #if defined(CONFIG_I2C_MUX)
1190 static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1191 {
1192 int ret=0;
1193
1194 if (argc == 1) {
1195 /* show all busses */
1196 I2C_MUX *mux;
1197 I2C_MUX_DEVICE *device = i2c_mux_devices;
1198
1199 printf ("Busses reached over muxes:\n");
1200 while (device != NULL) {
1201 printf ("Bus ID: %x\n", device->busid);
1202 printf (" reached over Mux(es):\n");
1203 mux = device->mux;
1204 while (mux != NULL) {
1205 printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
1206 mux = mux->next;
1207 }
1208 device = device->next;
1209 }
1210 } else {
1211 (void)i2c_mux_ident_muxstring ((uchar *)argv[1]);
1212 ret = 0;
1213 }
1214 return ret;
1215 }
1216 #endif /* CONFIG_I2C_MUX */
1217
1218 #if defined(CONFIG_I2C_MULTI_BUS)
1219 static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1220 {
1221 int bus_idx, ret=0;
1222
1223 if (argc == 1)
1224 /* querying current setting */
1225 printf("Current bus is %d\n", i2c_get_bus_num());
1226 else {
1227 bus_idx = simple_strtoul(argv[1], NULL, 10);
1228 printf("Setting bus to %d\n", bus_idx);
1229 ret = i2c_set_bus_num(bus_idx);
1230 if (ret)
1231 printf("Failure changing bus number (%d)\n", ret);
1232 }
1233 return ret;
1234 }
1235 #endif /* CONFIG_I2C_MULTI_BUS */
1236
1237 static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1238 {
1239 int speed, ret=0;
1240
1241 if (argc == 1)
1242 /* querying current speed */
1243 printf("Current bus speed=%d\n", i2c_get_bus_speed());
1244 else {
1245 speed = simple_strtoul(argv[1], NULL, 10);
1246 printf("Setting bus speed to %d Hz\n", speed);
1247 ret = i2c_set_bus_speed(speed);
1248 if (ret)
1249 printf("Failure changing bus speed (%d)\n", ret);
1250 }
1251 return ret;
1252 }
1253
1254 static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1255 {
1256 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1257 }
1258
1259 static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1260 {
1261 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1262 }
1263
1264 static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1265 {
1266 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1267 return 0;
1268 }
1269
1270 static cmd_tbl_t cmd_i2c_sub[] = {
1271 #if defined(CONFIG_I2C_MUX)
1272 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
1273 #endif /* CONFIG_I2C_MUX */
1274 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
1275 #if defined(CONFIG_I2C_MULTI_BUS)
1276 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
1277 #endif /* CONFIG_I2C_MULTI_BUS */
1278 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1279 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1280 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1281 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1282 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1283 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
1284 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
1285 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
1286 #if defined(CONFIG_CMD_SDRAM)
1287 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
1288 #endif
1289 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1290 };
1291
1292 #ifdef CONFIG_NEEDS_MANUAL_RELOC
1293 void i2c_reloc(void) {
1294 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1295 }
1296 #endif
1297
1298 static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1299 {
1300 cmd_tbl_t *c;
1301
1302 if (argc < 2)
1303 return cmd_usage(cmdtp);
1304
1305 /* Strip off leading 'i2c' command argument */
1306 argc--;
1307 argv++;
1308
1309 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1310
1311 if (c)
1312 return c->cmd(cmdtp, flag, argc, argv);
1313 else
1314 return cmd_usage(cmdtp);
1315 }
1316
1317 /***************************************************/
1318
1319 U_BOOT_CMD(
1320 i2c, 6, 1, do_i2c,
1321 "I2C sub-system",
1322 #if defined(CONFIG_I2C_MUX)
1323 "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
1324 #endif /* CONFIG_I2C_MUX */
1325 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
1326 #if defined(CONFIG_I2C_MULTI_BUS)
1327 "i2c dev [dev] - show or set current I2C bus\n"
1328 #endif /* CONFIG_I2C_MULTI_BUS */
1329 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
1330 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1331 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1332 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1333 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
1334 "i2c probe - show devices on the I2C bus\n"
1335 "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
1336 "i2c reset - re-init the I2C Controller\n"
1337 #if defined(CONFIG_CMD_SDRAM)
1338 "i2c sdram chip - print SDRAM configuration information\n"
1339 #endif
1340 "i2c speed [speed] - show or set I2C bus speed"
1341 );
1342
1343 #if defined(CONFIG_I2C_MUX)
1344 static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
1345 {
1346 I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
1347
1348 if (i2c_mux_devices == NULL) {
1349 i2c_mux_devices = dev;
1350 return 0;
1351 }
1352 while (devtmp->next != NULL)
1353 devtmp = devtmp->next;
1354
1355 devtmp->next = dev;
1356 return 0;
1357 }
1358
1359 I2C_MUX_DEVICE *i2c_mux_search_device(int id)
1360 {
1361 I2C_MUX_DEVICE *device = i2c_mux_devices;
1362
1363 while (device != NULL) {
1364 if (device->busid == id)
1365 return device;
1366 device = device->next;
1367 }
1368 return NULL;
1369 }
1370
1371 /* searches in the buf from *pos the next ':'.
1372 * returns:
1373 * 0 if found (with *pos = where)
1374 * < 0 if an error occured
1375 * > 0 if the end of buf is reached
1376 */
1377 static int i2c_mux_search_next (int *pos, uchar *buf, int len)
1378 {
1379 while ((buf[*pos] != ':') && (*pos < len)) {
1380 *pos += 1;
1381 }
1382 if (*pos >= len)
1383 return 1;
1384 if (buf[*pos] != ':')
1385 return -1;
1386 return 0;
1387 }
1388
1389 static int i2c_mux_get_busid (void)
1390 {
1391 int tmp = i2c_mux_busid;
1392
1393 i2c_mux_busid ++;
1394 return tmp;
1395 }
1396
1397 /* Analyses a Muxstring and immediately sends the
1398 commands to the muxes. Runs from flash.
1399 */
1400 int i2c_mux_ident_muxstring_f (uchar *buf)
1401 {
1402 int pos = 0;
1403 int oldpos;
1404 int ret = 0;
1405 int len = strlen((char *)buf);
1406 int chip;
1407 uchar channel;
1408 int was = 0;
1409
1410 while (ret == 0) {
1411 oldpos = pos;
1412 /* search name */
1413 ret = i2c_mux_search_next(&pos, buf, len);
1414 if (ret != 0)
1415 printf ("ERROR\n");
1416 /* search address */
1417 pos ++;
1418 oldpos = pos;
1419 ret = i2c_mux_search_next(&pos, buf, len);
1420 if (ret != 0)
1421 printf ("ERROR\n");
1422 buf[pos] = 0;
1423 chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1424 buf[pos] = ':';
1425 /* search channel */
1426 pos ++;
1427 oldpos = pos;
1428 ret = i2c_mux_search_next(&pos, buf, len);
1429 if (ret < 0)
1430 printf ("ERROR\n");
1431 was = 0;
1432 if (buf[pos] != 0) {
1433 buf[pos] = 0;
1434 was = 1;
1435 }
1436 channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1437 if (was)
1438 buf[pos] = ':';
1439 if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
1440 printf ("Error setting Mux: chip:%x channel: \
1441 %x\n", chip, channel);
1442 return -1;
1443 }
1444 pos ++;
1445 oldpos = pos;
1446
1447 }
1448
1449 return 0;
1450 }
1451
1452 /* Analyses a Muxstring and if this String is correct
1453 * adds a new I2C Bus.
1454 */
1455 I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
1456 {
1457 I2C_MUX_DEVICE *device;
1458 I2C_MUX *mux;
1459 int pos = 0;
1460 int oldpos;
1461 int ret = 0;
1462 int len = strlen((char *)buf);
1463 int was = 0;
1464
1465 device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
1466 device->mux = NULL;
1467 device->busid = i2c_mux_get_busid ();
1468 device->next = NULL;
1469 while (ret == 0) {
1470 mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
1471 mux->next = NULL;
1472 /* search name of mux */
1473 oldpos = pos;
1474 ret = i2c_mux_search_next(&pos, buf, len);
1475 if (ret != 0)
1476 printf ("%s no name.\n", __FUNCTION__);
1477 mux->name = (char *)malloc (pos - oldpos + 1);
1478 memcpy (mux->name, &buf[oldpos], pos - oldpos);
1479 mux->name[pos - oldpos] = 0;
1480 /* search address */
1481 pos ++;
1482 oldpos = pos;
1483 ret = i2c_mux_search_next(&pos, buf, len);
1484 if (ret != 0)
1485 printf ("%s no mux address.\n", __FUNCTION__);
1486 buf[pos] = 0;
1487 mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1488 buf[pos] = ':';
1489 /* search channel */
1490 pos ++;
1491 oldpos = pos;
1492 ret = i2c_mux_search_next(&pos, buf, len);
1493 if (ret < 0)
1494 printf ("%s no mux channel.\n", __FUNCTION__);
1495 was = 0;
1496 if (buf[pos] != 0) {
1497 buf[pos] = 0;
1498 was = 1;
1499 }
1500 mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1501 if (was)
1502 buf[pos] = ':';
1503 if (device->mux == NULL)
1504 device->mux = mux;
1505 else {
1506 I2C_MUX *muxtmp = device->mux;
1507 while (muxtmp->next != NULL) {
1508 muxtmp = muxtmp->next;
1509 }
1510 muxtmp->next = mux;
1511 }
1512 pos ++;
1513 oldpos = pos;
1514 }
1515 if (ret > 0) {
1516 /* Add Device */
1517 i2c_mux_add_device (device);
1518 return device;
1519 }
1520
1521 return NULL;
1522 }
1523
1524 int i2x_mux_select_mux(int bus)
1525 {
1526 I2C_MUX_DEVICE *dev;
1527 I2C_MUX *mux;
1528
1529 if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
1530 /* select Default Mux Bus */
1531 #if defined(CONFIG_SYS_I2C_IVM_BUS)
1532 i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
1533 #else
1534 {
1535 unsigned char *buf;
1536 buf = (unsigned char *) getenv("EEprom_ivm");
1537 if (buf != NULL)
1538 i2c_mux_ident_muxstring_f (buf);
1539 }
1540 #endif
1541 return 0;
1542 }
1543 dev = i2c_mux_search_device(bus);
1544 if (dev == NULL)
1545 return -1;
1546
1547 mux = dev->mux;
1548 while (mux != NULL) {
1549 /* do deblocking on each level of mux, before mux config */
1550 i2c_init_board();
1551 if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
1552 printf ("Error setting Mux: chip:%x channel: \
1553 %x\n", mux->chip, mux->channel);
1554 return -1;
1555 }
1556 mux = mux->next;
1557 }
1558 /* do deblocking on each level of mux and after mux config */
1559 i2c_init_board();
1560 return 0;
1561 }
1562 #endif /* CONFIG_I2C_MUX */