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Standardize command usage messages with cmd_usage()
[people/ms/u-boot.git] / common / cmd_pci.c
1 /*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28 /*
29 * PCI routines
30 */
31
32 #include <common.h>
33 #include <command.h>
34 #include <asm/processor.h>
35 #include <asm/io.h>
36 #include <pci.h>
37
38 unsigned char ShortPCIListing = 1;
39
40 /*
41 * Follows routines for the output of infos about devices on PCI bus.
42 */
43
44 void pci_header_show(pci_dev_t dev);
45 void pci_header_show_brief(pci_dev_t dev);
46
47 /*
48 * Subroutine: pciinfo
49 *
50 * Description: Show information about devices on PCI bus.
51 * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
52 * the output will be more or less exhaustive.
53 *
54 * Inputs: bus_no the number of the bus to be scanned.
55 *
56 * Return: None
57 *
58 */
59 void pciinfo(int BusNum, int ShortPCIListing)
60 {
61 int Device;
62 int Function;
63 unsigned char HeaderType;
64 unsigned short VendorID;
65 pci_dev_t dev;
66
67 printf("Scanning PCI devices on bus %d\n", BusNum);
68
69 if (ShortPCIListing) {
70 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
71 printf("_____________________________________________________________\n");
72 }
73
74 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
75 HeaderType = 0;
76 VendorID = 0;
77 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
78 /*
79 * If this is not a multi-function device, we skip the rest.
80 */
81 if (Function && !(HeaderType & 0x80))
82 break;
83
84 dev = PCI_BDF(BusNum, Device, Function);
85
86 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
87 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
88 continue;
89
90 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
91
92 if (ShortPCIListing)
93 {
94 printf("%02x.%02x.%02x ", BusNum, Device, Function);
95 pci_header_show_brief(dev);
96 }
97 else
98 {
99 printf("\nFound PCI device %02x.%02x.%02x:\n",
100 BusNum, Device, Function);
101 pci_header_show(dev);
102 }
103 }
104 }
105 }
106
107 static char *pci_classes_str(u8 class)
108 {
109 switch (class) {
110 case PCI_CLASS_NOT_DEFINED:
111 return "Build before PCI Rev2.0";
112 break;
113 case PCI_BASE_CLASS_STORAGE:
114 return "Mass storage controller";
115 break;
116 case PCI_BASE_CLASS_NETWORK:
117 return "Network controller";
118 break;
119 case PCI_BASE_CLASS_DISPLAY:
120 return "Display controller";
121 break;
122 case PCI_BASE_CLASS_MULTIMEDIA:
123 return "Multimedia device";
124 break;
125 case PCI_BASE_CLASS_MEMORY:
126 return "Memory controller";
127 break;
128 case PCI_BASE_CLASS_BRIDGE:
129 return "Bridge device";
130 break;
131 case PCI_BASE_CLASS_COMMUNICATION:
132 return "Simple comm. controller";
133 break;
134 case PCI_BASE_CLASS_SYSTEM:
135 return "Base system peripheral";
136 break;
137 case PCI_BASE_CLASS_INPUT:
138 return "Input device";
139 break;
140 case PCI_BASE_CLASS_DOCKING:
141 return "Docking station";
142 break;
143 case PCI_BASE_CLASS_PROCESSOR:
144 return "Processor";
145 break;
146 case PCI_BASE_CLASS_SERIAL:
147 return "Serial bus controller";
148 break;
149 case PCI_BASE_CLASS_INTELLIGENT:
150 return "Intelligent controller";
151 break;
152 case PCI_BASE_CLASS_SATELLITE:
153 return "Satellite controller";
154 break;
155 case PCI_BASE_CLASS_CRYPT:
156 return "Cryptographic device";
157 break;
158 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
159 return "DSP";
160 break;
161 case PCI_CLASS_OTHERS:
162 return "Does not fit any class";
163 break;
164 default:
165 return "???";
166 break;
167 };
168 }
169
170 /*
171 * Subroutine: pci_header_show_brief
172 *
173 * Description: Reads and prints the header of the
174 * specified PCI device in short form.
175 *
176 * Inputs: dev Bus+Device+Function number
177 *
178 * Return: None
179 *
180 */
181 void pci_header_show_brief(pci_dev_t dev)
182 {
183 u16 vendor, device;
184 u8 class, subclass;
185
186 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
187 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
188 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
189 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
190
191 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
192 vendor, device,
193 pci_classes_str(class), subclass);
194 }
195
196 /*
197 * Subroutine: PCI_Header_Show
198 *
199 * Description: Reads the header of the specified PCI device.
200 *
201 * Inputs: BusDevFunc Bus+Device+Function number
202 *
203 * Return: None
204 *
205 */
206 void pci_header_show(pci_dev_t dev)
207 {
208 u8 _byte, header_type;
209 u16 _word;
210 u32 _dword;
211
212 #define PRINT(msg, type, reg) \
213 pci_read_config_##type(dev, reg, &_##type); \
214 printf(msg, _##type)
215
216 #define PRINT2(msg, type, reg, func) \
217 pci_read_config_##type(dev, reg, &_##type); \
218 printf(msg, _##type, func(_##type))
219
220 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
221
222 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
223 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
224 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
225 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
226 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
227 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
228 pci_classes_str);
229 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
230 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
231 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
232 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
233 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
234 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
235 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
236
237 switch (header_type & 0x03) {
238 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
239 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
240 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
241 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
242 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
243 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
244 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
245 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
246 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
247 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
248 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
249 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
250 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
251 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
252 break;
253
254 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
255
256 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
257 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
258 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
259 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
260 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
261 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
262 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
263 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
264 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
265 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
266 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
267 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
268 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
269 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
270 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
271 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
272 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
273 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
274 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
275 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
276 break;
277
278 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
279
280 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
281 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
282 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
283 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
284 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
285 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
286 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
287 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
288 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
289 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
290 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
291 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
292 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
293 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
294 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
295 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
296 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
297 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
298 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
299 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
300 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
301 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
302 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
303 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
304 break;
305
306 default:
307 printf("unknown header\n");
308 break;
309 }
310
311 #undef PRINT
312 #undef PRINT2
313 }
314
315 /* Convert the "bus.device.function" identifier into a number.
316 */
317 static pci_dev_t get_pci_dev(char* name)
318 {
319 char cnum[12];
320 int len, i, iold, n;
321 int bdfs[3] = {0,0,0};
322
323 len = strlen(name);
324 if (len > 8)
325 return -1;
326 for (i = 0, iold = 0, n = 0; i < len; i++) {
327 if (name[i] == '.') {
328 memcpy(cnum, &name[iold], i - iold);
329 cnum[i - iold] = '\0';
330 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
331 iold = i + 1;
332 }
333 }
334 strcpy(cnum, &name[iold]);
335 if (n == 0)
336 n = 1;
337 bdfs[n] = simple_strtoul(cnum, NULL, 16);
338 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
339 }
340
341 static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
342 {
343 #define DISP_LINE_LEN 16
344 ulong i, nbytes, linebytes;
345 int rc = 0;
346
347 if (length == 0)
348 length = 0x40 / size; /* Standard PCI configuration space */
349
350 /* Print the lines.
351 * once, and all accesses are with the specified bus width.
352 */
353 nbytes = length * size;
354 do {
355 uint val4;
356 ushort val2;
357 u_char val1;
358
359 printf("%08lx:", addr);
360 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
361 for (i=0; i<linebytes; i+= size) {
362 if (size == 4) {
363 pci_read_config_dword(bdf, addr, &val4);
364 printf(" %08x", val4);
365 } else if (size == 2) {
366 pci_read_config_word(bdf, addr, &val2);
367 printf(" %04x", val2);
368 } else {
369 pci_read_config_byte(bdf, addr, &val1);
370 printf(" %02x", val1);
371 }
372 addr += size;
373 }
374 printf("\n");
375 nbytes -= linebytes;
376 if (ctrlc()) {
377 rc = 1;
378 break;
379 }
380 } while (nbytes > 0);
381
382 return (rc);
383 }
384
385 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
386 {
387 if (size == 4) {
388 pci_write_config_dword(bdf, addr, value);
389 }
390 else if (size == 2) {
391 ushort val = value & 0xffff;
392 pci_write_config_word(bdf, addr, val);
393 }
394 else {
395 u_char val = value & 0xff;
396 pci_write_config_byte(bdf, addr, val);
397 }
398 return 0;
399 }
400
401 static int
402 pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
403 {
404 ulong i;
405 int nbytes;
406 extern char console_buffer[];
407 uint val4;
408 ushort val2;
409 u_char val1;
410
411 /* Print the address, followed by value. Then accept input for
412 * the next value. A non-converted value exits.
413 */
414 do {
415 printf("%08lx:", addr);
416 if (size == 4) {
417 pci_read_config_dword(bdf, addr, &val4);
418 printf(" %08x", val4);
419 }
420 else if (size == 2) {
421 pci_read_config_word(bdf, addr, &val2);
422 printf(" %04x", val2);
423 }
424 else {
425 pci_read_config_byte(bdf, addr, &val1);
426 printf(" %02x", val1);
427 }
428
429 nbytes = readline (" ? ");
430 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
431 /* <CR> pressed as only input, don't modify current
432 * location and move to next. "-" pressed will go back.
433 */
434 if (incrflag)
435 addr += nbytes ? -size : size;
436 nbytes = 1;
437 #ifdef CONFIG_BOOT_RETRY_TIME
438 reset_cmd_timeout(); /* good enough to not time out */
439 #endif
440 }
441 #ifdef CONFIG_BOOT_RETRY_TIME
442 else if (nbytes == -2) {
443 break; /* timed out, exit the command */
444 }
445 #endif
446 else {
447 char *endp;
448 i = simple_strtoul(console_buffer, &endp, 16);
449 nbytes = endp - console_buffer;
450 if (nbytes) {
451 #ifdef CONFIG_BOOT_RETRY_TIME
452 /* good enough to not time out
453 */
454 reset_cmd_timeout();
455 #endif
456 pci_cfg_write (bdf, addr, size, i);
457 if (incrflag)
458 addr += size;
459 }
460 }
461 } while (nbytes);
462
463 return 0;
464 }
465
466 /* PCI Configuration Space access commands
467 *
468 * Syntax:
469 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
470 * pci next[.b, .w, .l] bus.device.function [addr]
471 * pci modify[.b, .w, .l] bus.device.function [addr]
472 * pci write[.b, .w, .l] bus.device.function addr value
473 */
474 int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
475 {
476 ulong addr = 0, value = 0, size = 0;
477 pci_dev_t bdf = 0;
478 char cmd = 's';
479
480 if (argc > 1)
481 cmd = argv[1][0];
482
483 switch (cmd) {
484 case 'd': /* display */
485 case 'n': /* next */
486 case 'm': /* modify */
487 case 'w': /* write */
488 /* Check for a size specification. */
489 size = cmd_get_data_size(argv[1], 4);
490 if (argc > 3)
491 addr = simple_strtoul(argv[3], NULL, 16);
492 if (argc > 4)
493 value = simple_strtoul(argv[4], NULL, 16);
494 case 'h': /* header */
495 if (argc < 3)
496 goto usage;
497 if ((bdf = get_pci_dev(argv[2])) == -1)
498 return 1;
499 break;
500 default: /* scan bus */
501 value = 1; /* short listing */
502 bdf = 0; /* bus number */
503 if (argc > 1) {
504 if (argv[argc-1][0] == 'l') {
505 value = 0;
506 argc--;
507 }
508 if (argc > 1)
509 bdf = simple_strtoul(argv[1], NULL, 16);
510 }
511 pciinfo(bdf, value);
512 return 0;
513 }
514
515 switch (argv[1][0]) {
516 case 'h': /* header */
517 pci_header_show(bdf);
518 return 0;
519 case 'd': /* display */
520 return pci_cfg_display(bdf, addr, size, value);
521 case 'n': /* next */
522 if (argc < 4)
523 goto usage;
524 return pci_cfg_modify(bdf, addr, size, value, 0);
525 case 'm': /* modify */
526 if (argc < 4)
527 goto usage;
528 return pci_cfg_modify(bdf, addr, size, value, 1);
529 case 'w': /* write */
530 if (argc < 5)
531 goto usage;
532 return pci_cfg_write(bdf, addr, size, value);
533 }
534
535 return 1;
536 usage:
537 cmd_usage(cmdtp);
538 return 1;
539 }
540
541 /***************************************************/
542
543
544 U_BOOT_CMD(
545 pci, 5, 1, do_pci,
546 "pci - list and access PCI Configuration Space\n",
547 "[bus] [long]\n"
548 " - short or long list of PCI devices on bus 'bus'\n"
549 "pci header b.d.f\n"
550 " - show header of PCI device 'bus.device.function'\n"
551 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
552 " - display PCI configuration space (CFG)\n"
553 "pci next[.b, .w, .l] b.d.f address\n"
554 " - modify, read and keep CFG address\n"
555 "pci modify[.b, .w, .l] b.d.f address\n"
556 " - modify, auto increment CFG address\n"
557 "pci write[.b, .w, .l] b.d.f address value\n"
558 " - write to CFG address\n"
559 );
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