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* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
[people/ms/u-boot.git] / common / cmd_pci.c
1 /*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28 /*
29 * PCI routines
30 */
31
32 #include <common.h>
33
34 #ifdef CONFIG_PCI
35
36 #include <command.h>
37 #include <cmd_boot.h>
38 #include <asm/processor.h>
39 #include <asm/io.h>
40 #include <cmd_pci.h>
41 #include <pci.h>
42
43 #if (CONFIG_COMMANDS & CFG_CMD_PCI)
44
45 extern int cmd_get_data_size(char* arg, int default_size);
46
47 unsigned char ShortPCIListing = 1;
48
49 /*
50 * Follows routines for the output of infos about devices on PCI bus.
51 */
52
53 void pci_header_show(pci_dev_t dev);
54 void pci_header_show_brief(pci_dev_t dev);
55
56 /*
57 * Subroutine: pciinfo
58 *
59 * Description: Show information about devices on PCI bus.
60 * Depending on the define CFG_SHORT_PCI_LISTING
61 * the output will be more or less exhaustive.
62 *
63 * Inputs: bus_no the number of the bus to be scanned.
64 *
65 * Return: None
66 *
67 */
68 void pciinfo(int BusNum, int ShortPCIListing)
69 {
70 int Device;
71 int Function;
72 unsigned char HeaderType;
73 unsigned short VendorID;
74 pci_dev_t dev;
75
76 printf("Scanning PCI devices on bus %d\n", BusNum);
77
78 if (ShortPCIListing) {
79 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
80 printf("_____________________________________________________________\n");
81 }
82
83 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
84 HeaderType = 0;
85 VendorID = 0;
86 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
87 /*
88 * If this is not a multi-function device, we skip the rest.
89 */
90 if (Function && !(HeaderType & 0x80))
91 break;
92
93 dev = PCI_BDF(BusNum, Device, Function);
94
95 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
96 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
97 continue;
98
99 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
100
101 if (ShortPCIListing)
102 {
103 printf("%02x.%02x.%02x ", BusNum, Device, Function);
104 pci_header_show_brief(dev);
105 }
106 else
107 {
108 printf("\nFound PCI device %02x.%02x.%02x:\n",
109 BusNum, Device, Function);
110 pci_header_show(dev);
111 }
112 }
113 }
114 }
115
116 static char *pci_classes_str(u8 class)
117 {
118 switch (class) {
119 case PCI_CLASS_NOT_DEFINED:
120 return "Build before PCI Rev2.0";
121 break;
122 case PCI_BASE_CLASS_STORAGE:
123 return "Mass storage controller";
124 break;
125 case PCI_BASE_CLASS_NETWORK:
126 return "Network controller";
127 break;
128 case PCI_BASE_CLASS_DISPLAY:
129 return "Display controller";
130 break;
131 case PCI_BASE_CLASS_MULTIMEDIA:
132 return "Multimedia device";
133 break;
134 case PCI_BASE_CLASS_MEMORY:
135 return "Memory controller";
136 break;
137 case PCI_BASE_CLASS_BRIDGE:
138 return "Bridge device";
139 break;
140 case PCI_BASE_CLASS_COMMUNICATION:
141 return "Simple comm. controller";
142 break;
143 case PCI_BASE_CLASS_SYSTEM:
144 return "Base system peripheral";
145 break;
146 case PCI_BASE_CLASS_INPUT:
147 return "Input device";
148 break;
149 case PCI_BASE_CLASS_DOCKING:
150 return "Docking station";
151 break;
152 case PCI_BASE_CLASS_PROCESSOR:
153 return "Processor";
154 break;
155 case PCI_BASE_CLASS_SERIAL:
156 return "Serial bus controller";
157 break;
158 case PCI_BASE_CLASS_INTELLIGENT:
159 return "Intelligent controller";
160 break;
161 case PCI_BASE_CLASS_SATELLITE:
162 return "Satellite controller";
163 break;
164 case PCI_BASE_CLASS_CRYPT:
165 return "Cryptographic device";
166 break;
167 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
168 return "DSP";
169 break;
170 case PCI_CLASS_OTHERS:
171 return "Does not fit any class";
172 break;
173 default:
174 return "???";
175 break;
176 };
177 }
178
179 /*
180 * Subroutine: pci_header_show_brief
181 *
182 * Description: Reads and prints the header of the
183 * specified PCI device in short form.
184 *
185 * Inputs: dev Bus+Device+Function number
186 *
187 * Return: None
188 *
189 */
190 void pci_header_show_brief(pci_dev_t dev)
191 {
192 u16 vendor, device;
193 u8 class, subclass;
194
195 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
196 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
197 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
198 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
199
200 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
201 vendor, device,
202 pci_classes_str(class), subclass);
203 }
204
205 /*
206 * Subroutine: PCI_Header_Show
207 *
208 * Description: Reads the header of the specified PCI device.
209 *
210 * Inputs: BusDevFunc Bus+Device+Function number
211 *
212 * Return: None
213 *
214 */
215 void pci_header_show(pci_dev_t dev)
216 {
217 u8 _byte, header_type;
218 u16 _word;
219 u32 _dword;
220
221 #define PRINT(msg, type, reg) \
222 pci_read_config_##type(dev, reg, &_##type); \
223 printf(msg, _##type)
224
225 #define PRINT2(msg, type, reg, func) \
226 pci_read_config_##type(dev, reg, &_##type); \
227 printf(msg, _##type, func(_##type))
228
229 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
230
231 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
232 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
233 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
234 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
235 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
236 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
237 pci_classes_str);
238 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
239 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
240 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
241 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
242 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
243 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
244 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
245
246 switch (header_type & 0x03) {
247 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
248 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
249 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
250 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
251 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
252 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
253 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
254 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
255 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
256 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
257 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
258 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
259 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
260 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
261 break;
262
263 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
264
265 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
266 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
267 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
268 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
269 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
270 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
271 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
272 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
273 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
274 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
275 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
276 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
277 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
278 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
279 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
280 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
281 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
282 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
283 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
284 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
285 break;
286
287 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
288
289 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
290 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
291 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
292 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
293 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
294 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
295 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
296 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
297 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
298 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
299 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
300 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
301 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
302 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
303 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
304 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
305 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
306 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
307 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
308 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
309 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
310 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
311 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
312 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
313 break;
314
315 default:
316 printf("unknown header\n");
317 break;
318 }
319
320 #undef PRINT
321 #undef PRINT2
322 }
323
324 /* Convert the "bus.device.function" identifier into a number.
325 */
326 static pci_dev_t get_pci_dev(char* name)
327 {
328 char cnum[12];
329 int len, i, iold, n;
330 int bdfs[3] = {0,0,0};
331
332 len = strlen(name);
333 if (len > 8)
334 return -1;
335 for (i = 0, iold = 0, n = 0; i < len; i++) {
336 if (name[i] == '.') {
337 memcpy(cnum, &name[iold], i - iold);
338 cnum[i - iold] = '\0';
339 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
340 iold = i + 1;
341 }
342 }
343 strcpy(cnum, &name[iold]);
344 if (n == 0)
345 n = 1;
346 bdfs[n] = simple_strtoul(cnum, NULL, 16);
347 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
348 }
349
350 static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
351 {
352 #define DISP_LINE_LEN 16
353 ulong i, nbytes, linebytes;
354 int rc = 0;
355
356 if (length == 0)
357 length = 0x40 / size; /* Standard PCI configuration space */
358
359 /* Print the lines.
360 * once, and all accesses are with the specified bus width.
361 */
362 nbytes = length * size;
363 do {
364 uint val4;
365 ushort val2;
366 u_char val1;
367
368 printf("%08lx:", addr);
369 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
370 for (i=0; i<linebytes; i+= size) {
371 if (size == 4) {
372 pci_read_config_dword(bdf, addr, &val4);
373 printf(" %08x", val4);
374 } else if (size == 2) {
375 pci_read_config_word(bdf, addr, &val2);
376 printf(" %04x", val2);
377 } else {
378 pci_read_config_byte(bdf, addr, &val1);
379 printf(" %02x", val1);
380 }
381 addr += size;
382 }
383 printf("\n");
384 nbytes -= linebytes;
385 if (ctrlc()) {
386 rc = 1;
387 break;
388 }
389 } while (nbytes > 0);
390
391 return (rc);
392 }
393
394 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
395 {
396 if (size == 4) {
397 pci_write_config_dword(bdf, addr, value);
398 }
399 else if (size == 2) {
400 ushort val = value & 0xffff;
401 pci_write_config_word(bdf, addr, val);
402 }
403 else {
404 u_char val = value & 0xff;
405 pci_write_config_byte(bdf, addr, val);
406 }
407 return 0;
408 }
409
410 static int
411 pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
412 {
413 ulong i;
414 int nbytes;
415 extern char console_buffer[];
416 uint val4;
417 ushort val2;
418 u_char val1;
419
420 /* Print the address, followed by value. Then accept input for
421 * the next value. A non-converted value exits.
422 */
423 do {
424 printf("%08lx:", addr);
425 if (size == 4) {
426 pci_read_config_dword(bdf, addr, &val4);
427 printf(" %08x", val4);
428 }
429 else if (size == 2) {
430 pci_read_config_word(bdf, addr, &val2);
431 printf(" %04x", val2);
432 }
433 else {
434 pci_read_config_byte(bdf, addr, &val1);
435 printf(" %02x", val1);
436 }
437
438 nbytes = readline (" ? ");
439 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
440 /* <CR> pressed as only input, don't modify current
441 * location and move to next. "-" pressed will go back.
442 */
443 if (incrflag)
444 addr += nbytes ? -size : size;
445 nbytes = 1;
446 #ifdef CONFIG_BOOT_RETRY_TIME
447 reset_cmd_timeout(); /* good enough to not time out */
448 #endif
449 }
450 #ifdef CONFIG_BOOT_RETRY_TIME
451 else if (nbytes == -2) {
452 break; /* timed out, exit the command */
453 }
454 #endif
455 else {
456 char *endp;
457 i = simple_strtoul(console_buffer, &endp, 16);
458 nbytes = endp - console_buffer;
459 if (nbytes) {
460 #ifdef CONFIG_BOOT_RETRY_TIME
461 /* good enough to not time out
462 */
463 reset_cmd_timeout();
464 #endif
465 pci_cfg_write (bdf, addr, size, i);
466 if (incrflag)
467 addr += size;
468 }
469 }
470 } while (nbytes);
471
472 return 0;
473 }
474
475 /* PCI Configuration Space access commands
476 *
477 * Syntax:
478 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
479 * pci next[.b, .w, .l] bus.device.function [addr]
480 * pci modify[.b, .w, .l] bus.device.function [addr]
481 * pci write[.b, .w, .l] bus.device.function addr value
482 */
483 int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
484 {
485 ulong addr = 0, value = 0, size = 0;
486 pci_dev_t bdf = 0;
487 char cmd = 's';
488
489 if (argc > 1)
490 cmd = argv[1][0];
491
492 switch (cmd) {
493 case 'd': /* display */
494 case 'n': /* next */
495 case 'm': /* modify */
496 case 'w': /* write */
497 /* Check for a size specification. */
498 size = cmd_get_data_size(argv[1], 4);
499 if (argc > 3)
500 addr = simple_strtoul(argv[3], NULL, 16);
501 if (argc > 4)
502 value = simple_strtoul(argv[4], NULL, 16);
503 case 'h': /* header */
504 if (argc < 3)
505 goto usage;
506 if ((bdf = get_pci_dev(argv[2])) == -1)
507 return 1;
508 break;
509 default: /* scan bus */
510 value = 1; /* short listing */
511 bdf = 0; /* bus number */
512 if (argc > 1) {
513 if (argv[argc-1][0] == 'l') {
514 value = 0;
515 argc--;
516 }
517 if (argc > 1)
518 bdf = simple_strtoul(argv[1], NULL, 16);
519 }
520 pciinfo(bdf, value);
521 return 0;
522 }
523
524 switch (argv[1][0]) {
525 case 'h': /* header */
526 pci_header_show(bdf);
527 return 0;
528 case 'd': /* display */
529 return pci_cfg_display(bdf, addr, size, value);
530 case 'n': /* next */
531 if (argc < 4)
532 goto usage;
533 return pci_cfg_modify(bdf, addr, size, value, 0);
534 case 'm': /* modify */
535 if (argc < 4)
536 goto usage;
537 return pci_cfg_modify(bdf, addr, size, value, 1);
538 case 'w': /* write */
539 if (argc < 5)
540 goto usage;
541 return pci_cfg_write(bdf, addr, size, value);
542 }
543
544 return 1;
545 usage:
546 printf ("Usage:\n%s\n", cmdtp->usage);
547 return 1;
548 }
549
550 #endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */
551
552 #endif /* CONFIG_PCI */
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