common/cmd_reginfo.c

   1 /*
   2  * (C) Copyright 2000
   3  * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #if defined(CONFIG_8xx)
  27 #include <mpc8xx.h>
  28 #elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
  29 #include <asm/processor.h>
  30 #elif defined (CONFIG_5xx)
  31 #include <mpc5xx.h>
  32 #elif defined (CONFIG_MPC5200)
  33 #include <mpc5xxx.h>
  34 #elif defined (CONFIG_MPC86xx)
  35 extern void mpc86xx_reginfo(void);
  36 #endif
  37
  38 int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  39 {
  40 #if defined(CONFIG_8xx)
  41         volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
  42         volatile memctl8xx_t *memctl = &immap->im_memctl;
  43         volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
  44         volatile sit8xx_t *timers = &immap->im_sit;
  45
  46         /* Hopefully more PowerPC  knowledgable people will add code to display
  47          * other useful registers
  48          */
  49
  50         printf ("\nSystem Configuration registers\n"
  51
  52                 "\tIMMR\t0x%08X\n", get_immr(0));
  53
  54         printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
  55         printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
  56
  57         printf("\tSWT\t0x%08X",    sysconf->sc_swt);
  58         printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
  59
  60         printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
  61                 sysconf->sc_sipend, sysconf->sc_simask);
  62         printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
  63                 sysconf->sc_siel, sysconf->sc_sivec);
  64         printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
  65                 sysconf->sc_tesr, sysconf->sc_sdcr);
  66
  67         printf ("Memory Controller Registers\n"
  68
  69                 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
  70         printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
  71         printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
  72         printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
  73         printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
  74         printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
  75         printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
  76         printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
  77         printf ("\n"
  78                 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
  79                 memctl->memc_mamr, memctl->memc_mbmr );
  80         printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
  81                 memctl->memc_mstat, memctl->memc_mptpr );
  82         printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
  83
  84         printf ("\nSystem Integration Timers\n"
  85                 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
  86                 timers->sit_tbscr, timers->sit_rtcsc);
  87         printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
  88
  89         /*
  90          * May be some CPM info here?
  91          */
  92
  93 #elif defined (CONFIG_405GP)
  94         printf ("\n405GP registers; MSR=%08x\n",mfmsr());
  95         printf ("\nUniversal Interrupt Controller Regs\n"
  96             "uicsr    uicsrs   uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
  97             "\n"
  98             "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
  99         mfdcr(uicsr),
 100         mfdcr(uicsrs),
 101         mfdcr(uicer),
 102         mfdcr(uiccr),
 103         mfdcr(uicpr),
 104         mfdcr(uictr),
 105         mfdcr(uicmsr),
 106         mfdcr(uicvr),
 107         mfdcr(uicvcr));
 108
 109         puts ("\nMemory (SDRAM) Configuration\n"
 110             "besra    besrsa   besrb    besrsb   bear     mcopt1   rtr      pmit\n");
 111
 112         mtdcr(memcfga,mem_besra);       printf ("%08x ", mfdcr(memcfgd));
 113         mtdcr(memcfga,mem_besrsa);      printf ("%08x ", mfdcr(memcfgd));
 114         mtdcr(memcfga,mem_besrb);       printf ("%08x ", mfdcr(memcfgd));
 115         mtdcr(memcfga,mem_besrsb);      printf ("%08x ", mfdcr(memcfgd));
 116         mtdcr(memcfga,mem_bear);        printf ("%08x ", mfdcr(memcfgd));
 117         mtdcr(memcfga,mem_mcopt1);      printf ("%08x ", mfdcr(memcfgd));
 118         mtdcr(memcfga,mem_rtr);         printf ("%08x ", mfdcr(memcfgd));
 119         mtdcr(memcfga,mem_pmit);        printf ("%08x ", mfdcr(memcfgd));
 120
 121         puts ("\n"
 122             "mb0cf    mb1cf    mb2cf    mb3cf    sdtr1    ecccf    eccerr\n");
 123         mtdcr(memcfga,mem_mb0cf);       printf ("%08x ", mfdcr(memcfgd));
 124         mtdcr(memcfga,mem_mb1cf);       printf ("%08x ", mfdcr(memcfgd));
 125         mtdcr(memcfga,mem_mb2cf);       printf ("%08x ", mfdcr(memcfgd));
 126         mtdcr(memcfga,mem_mb3cf);       printf ("%08x ", mfdcr(memcfgd));
 127         mtdcr(memcfga,mem_sdtr1);       printf ("%08x ", mfdcr(memcfgd));
 128         mtdcr(memcfga,mem_ecccf);       printf ("%08x ", mfdcr(memcfgd));
 129         mtdcr(memcfga,mem_eccerr);      printf ("%08x ", mfdcr(memcfgd));
 130
 131         printf ("\n\n"
 132             "DMA Channels\n"
 133             "dmasr    dmasgc   dmaadr\n"
 134             "%08x %08x %08x\n"
 135             "dmacr_0  dmact_0  dmada_0  dmasa_0  dmasb_0\n"
 136             "%08x %08x %08x %08x %08x\n"
 137             "dmacr_1  dmact_1  dmada_1  dmasa_1  dmasb_1\n"
 138             "%08x %08x %08x %08x %08x\n",
 139         mfdcr(dmasr),  mfdcr(dmasgc),mfdcr(dmaadr),
 140         mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
 141         mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
 142
 143         printf (
 144             "dmacr_2  dmact_2  dmada_2  dmasa_2  dmasb_2\n"     "%08x %08x %08x %08x %08x\n"
 145             "dmacr_3  dmact_3  dmada_3  dmasa_3  dmasb_3\n"     "%08x %08x %08x %08x %08x\n",
 146         mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
 147         mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
 148
 149         puts ("\n"
 150             "External Bus\n"
 151             "pbear    pbesr0   pbesr1   epcr\n");
 152         mtdcr(ebccfga,pbear);   printf ("%08x ", mfdcr(ebccfgd));
 153         mtdcr(ebccfga,pbesr0);  printf ("%08x ", mfdcr(ebccfgd));
 154         mtdcr(ebccfga,pbesr1);  printf ("%08x ", mfdcr(ebccfgd));
 155         mtdcr(ebccfga,epcr);    printf ("%08x ", mfdcr(ebccfgd));
 156
 157         puts ("\n"
 158             "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
 159         mtdcr(ebccfga,pb0cr);   printf ("%08x ", mfdcr(ebccfgd));
 160         mtdcr(ebccfga,pb0ap);   printf ("%08x ", mfdcr(ebccfgd));
 161         mtdcr(ebccfga,pb1cr);   printf ("%08x ", mfdcr(ebccfgd));
 162         mtdcr(ebccfga,pb1ap);   printf ("%08x ", mfdcr(ebccfgd));
 163         mtdcr(ebccfga,pb2cr);   printf ("%08x ", mfdcr(ebccfgd));
 164         mtdcr(ebccfga,pb2ap);   printf ("%08x ", mfdcr(ebccfgd));
 165         mtdcr(ebccfga,pb3cr);   printf ("%08x ", mfdcr(ebccfgd));
 166         mtdcr(ebccfga,pb3ap);   printf ("%08x ", mfdcr(ebccfgd));
 167
 168         puts ("\n"
 169             "pb4cr    pb4ap    pb5cr    bp5ap    pb6cr    pb6ap    pb7cr    pb7ap\n");
 170         mtdcr(ebccfga,pb4cr);   printf ("%08x ", mfdcr(ebccfgd));
 171         mtdcr(ebccfga,pb4ap);   printf ("%08x ", mfdcr(ebccfgd));
 172         mtdcr(ebccfga,pb5cr);   printf ("%08x ", mfdcr(ebccfgd));
 173         mtdcr(ebccfga,pb5ap);   printf ("%08x ", mfdcr(ebccfgd));
 174         mtdcr(ebccfga,pb6cr);   printf ("%08x ", mfdcr(ebccfgd));
 175         mtdcr(ebccfga,pb6ap);   printf ("%08x ", mfdcr(ebccfgd));
 176         mtdcr(ebccfga,pb7cr);   printf ("%08x ", mfdcr(ebccfgd));
 177         mtdcr(ebccfga,pb7ap);   printf ("%08x ", mfdcr(ebccfgd));
 178
 179         puts ("\n\n");
 180
 181 #elif defined(CONFIG_405EP)
 182         printf ("\n405EP registers; MSR=%08x\n",mfmsr());
 183         printf ("\nUniversal Interrupt Controller Regs\n"
 184             "uicsr    uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
 185             "\n"
 186             "%08x %08x %08x %08x %08x %08x %08x %08x\n",
 187         mfdcr(uicsr),
 188         mfdcr(uicer),
 189         mfdcr(uiccr),
 190         mfdcr(uicpr),
 191         mfdcr(uictr),
 192         mfdcr(uicmsr),
 193         mfdcr(uicvr),
 194         mfdcr(uicvcr));
 195
 196         puts ("\nMemory (SDRAM) Configuration\n"
 197             "mcopt1   rtr      pmit     mb0cf    mb1cf    sdtr1\n");
 198
 199         mtdcr(memcfga,mem_mcopt1);      printf ("%08x ", mfdcr(memcfgd));
 200         mtdcr(memcfga,mem_rtr);         printf ("%08x ", mfdcr(memcfgd));
 201         mtdcr(memcfga,mem_pmit);        printf ("%08x ", mfdcr(memcfgd));
 202         mtdcr(memcfga,mem_mb0cf);       printf ("%08x ", mfdcr(memcfgd));
 203         mtdcr(memcfga,mem_mb1cf);       printf ("%08x ", mfdcr(memcfgd));
 204         mtdcr(memcfga,mem_sdtr1);       printf ("%08x ", mfdcr(memcfgd));
 205
 206         printf ("\n\n"
 207             "DMA Channels\n"
 208             "dmasr    dmasgc   dmaadr\n"                        "%08x %08x %08x\n"
 209             "dmacr_0  dmact_0  dmada_0  dmasa_0  dmasb_0\n"     "%08x %08x %08x %08x %08x\n"
 210             "dmacr_1  dmact_1  dmada_1  dmasa_1  dmasb_1\n"     "%08x %08x %08x %08x %08x\n",
 211         mfdcr(dmasr),  mfdcr(dmasgc),mfdcr(dmaadr),
 212         mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
 213         mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
 214
 215         printf (
 216             "dmacr_2  dmact_2  dmada_2  dmasa_2  dmasb_2\n"     "%08x %08x %08x %08x %08x\n"
 217             "dmacr_3  dmact_3  dmada_3  dmasa_3  dmasb_3\n"     "%08x %08x %08x %08x %08x\n",
 218         mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
 219         mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
 220
 221         puts ("\n"
 222             "External Bus\n"
 223             "pbear    pbesr0   pbesr1   epcr\n");
 224         mtdcr(ebccfga,pbear);   printf ("%08x ", mfdcr(ebccfgd));
 225         mtdcr(ebccfga,pbesr0);  printf ("%08x ", mfdcr(ebccfgd));
 226         mtdcr(ebccfga,pbesr1);  printf ("%08x ", mfdcr(ebccfgd));
 227         mtdcr(ebccfga,epcr);    printf ("%08x ", mfdcr(ebccfgd));
 228
 229         puts ("\n"
 230             "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
 231         mtdcr(ebccfga,pb0cr);   printf ("%08x ", mfdcr(ebccfgd));
 232         mtdcr(ebccfga,pb0ap);   printf ("%08x ", mfdcr(ebccfgd));
 233         mtdcr(ebccfga,pb1cr);   printf ("%08x ", mfdcr(ebccfgd));
 234         mtdcr(ebccfga,pb1ap);   printf ("%08x ", mfdcr(ebccfgd));
 235         mtdcr(ebccfga,pb2cr);   printf ("%08x ", mfdcr(ebccfgd));
 236         mtdcr(ebccfga,pb2ap);   printf ("%08x ", mfdcr(ebccfgd));
 237         mtdcr(ebccfga,pb3cr);   printf ("%08x ", mfdcr(ebccfgd));
 238         mtdcr(ebccfga,pb3ap);   printf ("%08x ", mfdcr(ebccfgd));
 239
 240         puts ("\n"
 241             "pb4cr    pb4ap\n");
 242         mtdcr(ebccfga,pb4cr);   printf ("%08x ", mfdcr(ebccfgd));
 243         mtdcr(ebccfga,pb4ap);   printf ("%08x ", mfdcr(ebccfgd));
 244
 245         puts ("\n\n");
 246 #elif defined(CONFIG_5xx)
 247
 248         volatile immap_t        *immap  = (immap_t *)CFG_IMMR;
 249         volatile memctl5xx_t    *memctl = &immap->im_memctl;
 250         volatile sysconf5xx_t   *sysconf = &immap->im_siu_conf;
 251         volatile sit5xx_t       *timers = &immap->im_sit;
 252         volatile car5xx_t       *car = &immap->im_clkrst;
 253         volatile uimb5xx_t      *uimb = &immap->im_uimb;
 254
 255         puts ("\nSystem Configuration registers\n");
 256         printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
 257         printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
 258         printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
 259         printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
 260         printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
 261
 262         puts ("\nMemory Controller Registers\n");
 263         printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
 264         printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
 265         printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
 266         printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
 267         printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
 268         printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
 269
 270         puts ("\nSystem Integration Timers\n");
 271         printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
 272         printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
 273
 274         puts ("\nClocks and Reset\n");
 275         printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
 276
 277         puts ("\nU-Bus to IMB3 Bus Interface\n");
 278         printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
 279         puts ("\n\n");
 280
 281 #elif defined(CONFIG_MPC5200)
 282         puts ("\nMPC5200 registers\n");
 283         printf ("MBAR=%08x\n", CFG_MBAR);
 284         puts ("Memory map registers\n");
 285         printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 286                 *(volatile ulong*)MPC5XXX_CS0_START,
 287                 *(volatile ulong*)MPC5XXX_CS0_STOP,
 288                 *(volatile ulong*)MPC5XXX_CS0_CFG,
 289                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
 290         printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 291                 *(volatile ulong*)MPC5XXX_CS1_START,
 292                 *(volatile ulong*)MPC5XXX_CS1_STOP,
 293                 *(volatile ulong*)MPC5XXX_CS1_CFG,
 294                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
 295         printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 296                 *(volatile ulong*)MPC5XXX_CS2_START,
 297                 *(volatile ulong*)MPC5XXX_CS2_STOP,
 298                 *(volatile ulong*)MPC5XXX_CS2_CFG,
 299                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
 300         printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 301                 *(volatile ulong*)MPC5XXX_CS3_START,
 302                 *(volatile ulong*)MPC5XXX_CS3_STOP,
 303                 *(volatile ulong*)MPC5XXX_CS3_CFG,
 304                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
 305         printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 306                 *(volatile ulong*)MPC5XXX_CS4_START,
 307                 *(volatile ulong*)MPC5XXX_CS4_STOP,
 308                 *(volatile ulong*)MPC5XXX_CS4_CFG,
 309                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
 310         printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 311                 *(volatile ulong*)MPC5XXX_CS5_START,
 312                 *(volatile ulong*)MPC5XXX_CS5_STOP,
 313                 *(volatile ulong*)MPC5XXX_CS5_CFG,
 314                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
 315         printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 316                 *(volatile ulong*)MPC5XXX_CS6_START,
 317                 *(volatile ulong*)MPC5XXX_CS6_STOP,
 318                 *(volatile ulong*)MPC5XXX_CS6_CFG,
 319                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
 320         printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 321                 *(volatile ulong*)MPC5XXX_CS7_START,
 322                 *(volatile ulong*)MPC5XXX_CS7_STOP,
 323                 *(volatile ulong*)MPC5XXX_CS7_CFG,
 324                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
 325         printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n",
 326                 *(volatile ulong*)MPC5XXX_BOOTCS_START,
 327                 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
 328                 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
 329                 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
 330         printf ("\tSDRAMCS0: %08X\n",
 331                 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
 332         printf ("\tSDRAMCS1: %08X\n",
 333                 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
 334 #elif defined(CONFIG_MPC86xx)
 335         mpc86xx_reginfo();
 336
 337 #elif defined(CONFIG_BLACKFIN)
 338         puts("\nSystem Configuration registers\n");
 339
 340         puts("\nPLL Registers\n");
 341         printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
 342                 bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
 343         printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
 344                 bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
 345         printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());
 346
 347         puts("\nEBIU AMC Registers\n");
 348         printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
 349         printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
 350                 bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
 351 # ifdef EBIU_MODE
 352         printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
 353                 bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
 354         printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
 355                 bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
 356 # endif
 357
 358 # ifdef EBIU_RSTCTL
 359         puts("\nEBIU DDR Registers\n");
 360         printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
 361                 bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
 362         printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
 363                 bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
 364         printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
 365                 bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
 366         printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
 367                 bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
 368 # else
 369         puts("\nEBIU SDC Registers\n");
 370         printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
 371                 bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
 372         printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
 373                 bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
 374 # endif
 375
 376 #endif /* CONFIG_BLACKFIN */
 377
 378         return 0;
 379 }
 380
 381  /**************************************************/
 382
 383 #if defined(CONFIG_CMD_REGINFO)
 384 U_BOOT_CMD(
 385         reginfo,        2,      1,      do_reginfo,
 386         "reginfo - print register information\n",
 387 );
 388 #endif