]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/74xx_7xx/cpu.c
629ed66b07ec8769c2b96242475f75ec6c3d9994
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
35 * more modifications by
36 * Josh Huber <huber@mclx.com>
37 * added support for the 74xx series of cpus
38 * added support for the 7xx series of cpus
39 * made the code a little less hard-coded, and more auto-detectish
45 #include <asm/cache.h>
47 #ifdef CONFIG_AMIGAONEG3SE
48 #include "../board/MAI/AmigaOneG3SE/via686.h"
49 #include "../board/MAI/AmigaOneG3SE/memio.h"
60 switch (PVR_VER(pvr
)) {
67 if (((pvr
>> 8) & 0xff) == 0x01) {
68 type
= CPU_750CX
; /* old CX (80100 and 8010x?)*/
69 } else if (((pvr
>> 8) & 0xff) == 0x22) {
70 type
= CPU_750CX
; /* CX (82201,82202) and CXe (82214) */
71 } else if (((pvr
>> 8) & 0xff) == 0x33) {
72 type
= CPU_750CX
; /* CXe (83311) */
73 } else if (((pvr
>> 12) & 0xF) == 0x3) {
109 /* ------------------------------------------------------------------------- */
111 #if !defined(CONFIG_BAB7xx)
114 DECLARE_GLOBAL_DATA_PTR
;
116 uint type
= get_cpu_type();
117 uint pvr
= get_pvr();
118 ulong clock
= gd
->cpu_clk
;
126 printf ("750CX%s v%d.%d", (pvr
&0xf0)?"e":"",
168 printf("Unknown CPU -- PVR: 0x%08x\n", pvr
);
172 printf ("%s v%d.%d", str
, (pvr
>> 8) & 0xFF, pvr
& 0xFF);
174 printf (" @ %s MHz\n", strmhz(buf
, clock
));
179 /* these two functions are unimplemented currently [josh] */
181 /* -------------------------------------------------------------------- */
190 /* -------------------------------------------------------------------- */
199 /* -------------------------------------------------------------------- */
202 soft_restart(unsigned long addr
)
204 /* SRR0 has system reset vector, SRR1 has default MSR value */
205 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
207 __asm__
__volatile__ ("mtspr 26, %0" :: "r" (addr
));
208 __asm__
__volatile__ ("li 4, (1 << 6)" ::: "r4");
209 __asm__
__volatile__ ("mtspr 27, 4");
210 __asm__
__volatile__ ("rfi");
212 while(1); /* not reached */
216 #if !defined(CONFIG_PCIPPC2) && \
217 !defined(CONFIG_BAB7xx) && \
218 !defined(CONFIG_ELPPC)
219 /* no generic way to do board reset. simply call soft_reset. */
221 do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
224 /* flush and disable I/D cache */
225 __asm__
__volatile__ ("mfspr 3, 1008" ::: "r3");
226 __asm__
__volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
227 __asm__
__volatile__ ("ori 4, 3, 0xc00" ::: "r4");
228 __asm__
__volatile__ ("andc 5, 3, 5" ::: "r5");
229 __asm__
__volatile__ ("sync");
230 __asm__
__volatile__ ("mtspr 1008, 4");
231 __asm__
__volatile__ ("isync");
232 __asm__
__volatile__ ("sync");
233 __asm__
__volatile__ ("mtspr 1008, 5");
234 __asm__
__volatile__ ("isync");
235 __asm__
__volatile__ ("sync");
237 #ifdef CFG_RESET_ADDRESS
238 addr
= CFG_RESET_ADDRESS
;
241 * note: when CFG_MONITOR_BASE points to a RAM address,
242 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
243 * address. Better pick an address known to be invalid on your
244 * system and assign it to CFG_RESET_ADDRESS.
246 addr
= CFG_MONITOR_BASE
- sizeof (ulong
);
249 while(1); /* not reached */
253 /* ------------------------------------------------------------------------- */
256 * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
258 #ifdef CONFIG_AMIGAONEG3SE
259 unsigned long get_tbclk(void)
261 DECLARE_GLOBAL_DATA_PTR
;
263 return (gd
->bus_clk
/ 4);
265 #else /* ! CONFIG_AMIGAONEG3SE */
267 unsigned long get_tbclk (void)
269 return CFG_BUS_HZ
/ 4;
271 #endif /* CONFIG_AMIGAONEG3SE */
272 /* ------------------------------------------------------------------------- */
274 #if defined(CONFIG_WATCHDOG)
275 #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
281 #endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
282 #endif /* CONFIG_WATCHDOG */
284 /* ------------------------------------------------------------------------- */