cpu/arm1136/mx31/generic.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/arch/mx31-regs.h>
  26
  27 static u32 mx31_decode_pll(u32 reg, u32 infreq)
  28 {
  29         u32 mfi = (reg >> 10) & 0xf;
  30         u32 mfn = reg & 0x3ff;
  31         u32 mfd = (reg >> 16) & 0x3ff;
  32         u32 pd =  (reg >> 26) & 0xf;
  33
  34         mfi = mfi <= 5 ? 5 : mfi;
  35         mfd += 1;
  36         pd += 1;
  37
  38         return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
  39                 (mfd * pd)) << 10;
  40 }
  41
  42 static u32 mx31_get_mpl_dpdgck_clk(void)
  43 {
  44         u32 infreq;
  45
  46         if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
  47                 infreq = CONFIG_MX31_CLK32 * 1024;
  48         else
  49                 infreq = CONFIG_MX31_HCLK_FREQ;
  50
  51         return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
  52 }
  53
  54 static u32 mx31_get_mcu_main_clk(void)
  55 {
  56         /* For now we assume mpl_dpdgck_clk == mcu_main_clk
  57          * which should be correct for most boards
  58          */
  59         return mx31_get_mpl_dpdgck_clk();
  60 }
  61
  62 u32 mx31_get_ipg_clk(void)
  63 {
  64         u32 freq = mx31_get_mcu_main_clk();
  65         u32 pdr0 = __REG(CCM_PDR0);
  66
  67         freq /= ((pdr0 >> 3) & 0x7) + 1;
  68         freq /= ((pdr0 >> 6) & 0x3) + 1;
  69
  70         return freq;
  71 }
  72
  73 void mx31_dump_clocks(void)
  74 {
  75         u32 cpufreq = mx31_get_mcu_main_clk();
  76         printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
  77         printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
  78 }
  79
  80 void mx31_gpio_mux(unsigned long mode)
  81 {
  82         unsigned long reg, shift, tmp;
  83
  84         reg = IOMUXC_BASE + (mode & 0x1fc);
  85         shift = (~mode & 0x3) * 8;
  86
  87         tmp = __REG(reg);
  88         tmp &= ~(0xff << shift);
  89         tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
  90         __REG(reg) = tmp;
  91 }
  92
  93 #if defined(CONFIG_DISPLAY_CPUINFO)
  94 int print_cpuinfo (void)
  95 {
  96         printf("CPU:   Freescale i.MX31 at %d MHz\n",
  97                 mx31_get_mcu_main_clk() / 1000000);
  98         return 0;
  99 }
 100 #endif