cpu/arm1136/start.S

   1 /*
   2  *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
   3  *
   4  *  Copyright (c) 2004  Texas Instruments <r-woodruff2@ti.com>
   5  *
   6  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   7  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   8  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   9  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  10  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33 .globl _start
  34 _start: b       reset
  35 #ifdef CONFIG_ONENAND_IPL
  36         ldr     pc, _hang
  37         ldr     pc, _hang
  38         ldr     pc, _hang
  39         ldr     pc, _hang
  40         ldr     pc, _hang
  41         ldr     pc, _hang
  42         ldr     pc, _hang
  43
  44 _hang:
  45         .word   do_hang
  46         .word   0x12345678
  47         .word   0x12345678
  48         .word   0x12345678
  49         .word   0x12345678
  50         .word   0x12345678
  51         .word   0x12345678
  52         .word   0x12345678      /* now 16*4=64 */
  53 #else
  54         ldr     pc, _undefined_instruction
  55         ldr     pc, _software_interrupt
  56         ldr     pc, _prefetch_abort
  57         ldr     pc, _data_abort
  58         ldr     pc, _not_used
  59         ldr     pc, _irq
  60         ldr     pc, _fiq
  61
  62 _undefined_instruction: .word undefined_instruction
  63 _software_interrupt:    .word software_interrupt
  64 _prefetch_abort:        .word prefetch_abort
  65 _data_abort:            .word data_abort
  66 _not_used:              .word not_used
  67 _irq:                   .word irq
  68 _fiq:                   .word fiq
  69 _pad:                   .word 0x12345678 /* now 16*4=64 */
  70 #endif  /* CONFIG_ONENAND_IPL */
  71 .global _end_vect
  72 _end_vect:
  73
  74         .balignl 16,0xdeadbeef
  75 /*
  76  *************************************************************************
  77  *
  78  * Startup Code (reset vector)
  79  *
  80  * do important init only if we don't start from memory!
  81  * setup Memory and board specific bits prior to relocation.
  82  * relocate armboot to ram
  83  * setup stack
  84  *
  85  *************************************************************************
  86  */
  87
  88 _TEXT_BASE:
  89         .word   TEXT_BASE
  90
  91 .globl _armboot_start
  92 _armboot_start:
  93         .word _start
  94
  95 /*
  96  * These are defined in the board-specific linker script.
  97  */
  98 .globl _bss_start
  99 _bss_start:
 100         .word __bss_start
 101
 102 .globl _bss_end
 103 _bss_end:
 104         .word _end
 105
 106 #ifdef CONFIG_USE_IRQ
 107 /* IRQ stack memory (calculated at run-time) */
 108 .globl IRQ_STACK_START
 109 IRQ_STACK_START:
 110         .word   0x0badc0de
 111
 112 /* IRQ stack memory (calculated at run-time) */
 113 .globl FIQ_STACK_START
 114 FIQ_STACK_START:
 115         .word 0x0badc0de
 116 #endif
 117
 118 /*
 119  * the actual reset code
 120  */
 121
 122 reset:
 123         /*
 124          * set the cpu to SVC32 mode
 125          */
 126         mrs     r0,cpsr
 127         bic     r0,r0,#0x1f
 128         orr     r0,r0,#0xd3
 129         msr     cpsr,r0
 130
 131 #ifdef CONFIG_OMAP2420H4
 132        /* Copy vectors to mask ROM indirect addr */
 133         adr     r0, _start              /* r0 <- current position of code   */
 134                 add     r0, r0, #4                              /* skip reset vector                    */
 135         mov     r2, #64                 /* r2 <- size to copy  */
 136         add     r2, r0, r2              /* r2 <- source end address         */
 137         mov     r1, #SRAM_OFFSET0         /* build vect addr */
 138         mov     r3, #SRAM_OFFSET1
 139         add     r1, r1, r3
 140         mov     r3, #SRAM_OFFSET2
 141         add     r1, r1, r3
 142 next:
 143         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 144         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 145         cmp     r0, r2                  /* until source end address [r2]    */
 146         bne     next                    /* loop until equal */
 147         bl      cpy_clk_code            /* put dpll adjust code behind vectors */
 148 #endif
 149         /* the mask ROM code should have PLL and others stable */
 150 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 151         bl  cpu_init_crit
 152 #endif
 153
 154 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 155 relocate:                               /* relocate U-Boot to RAM           */
 156         adr     r0, _start              /* r0 <- current position of code   */
 157         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 158         cmp     r0, r1                  /* don't reloc during debug         */
 159 #ifndef CONFIG_ONENAND_IPL
 160         beq     stack_setup
 161 #endif  /* CONFIG_ONENAND_IPL */
 162
 163         ldr     r2, _armboot_start
 164         ldr     r3, _bss_start
 165         sub     r2, r3, r2              /* r2 <- size of armboot            */
 166         add     r2, r0, r2              /* r2 <- source end address         */
 167
 168 copy_loop:
 169         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 170         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 171         cmp     r0, r2                  /* until source end addreee [r2]    */
 172         ble     copy_loop
 173 #endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
 174
 175         /* Set up the stack                                                 */
 176 stack_setup:
 177         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 178 #ifdef CONFIG_ONENAND_IPL
 179         sub     sp, r0, #128            /* leave 32 words for abort-stack   */
 180 #else
 181         sub     r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area                       */
 182         sub     r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                         */
 183 #ifdef CONFIG_USE_IRQ
 184         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 185 #endif
 186         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 187 #endif  /* CONFIG_ONENAND_IPL */
 188
 189 clear_bss:
 190         ldr     r0, _bss_start          /* find start of bss segment        */
 191         ldr     r1, _bss_end            /* stop here                        */
 192         mov     r2, #0x00000000         /* clear                            */
 193
 194 #ifndef CONFIG_ONENAND_IPL
 195 clbss_l:str     r2, [r0]                /* clear loop...                    */
 196         add     r0, r0, #4
 197         cmp     r0, r1
 198         bne     clbss_l
 199 #endif
 200
 201         ldr     pc, _start_armboot
 202
 203 #ifdef CONFIG_ONENAND_IPL
 204 _start_armboot: .word start_oneboot
 205 #else
 206 _start_armboot: .word start_armboot
 207 #endif
 208
 209
 210 /*
 211  *************************************************************************
 212  *
 213  * CPU_init_critical registers
 214  *
 215  * setup important registers
 216  * setup memory timing
 217  *
 218  *************************************************************************
 219  */
 220 cpu_init_crit:
 221         /*
 222          * flush v4 I/D caches
 223          */
 224         mov     r0, #0
 225         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 226         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 227
 228         /*
 229          * disable MMU stuff and caches
 230          */
 231         mrc     p15, 0, r0, c1, c0, 0
 232         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 233         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 234         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 235         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 236         mcr     p15, 0, r0, c1, c0, 0
 237
 238         /*
 239          * Jump to board specific initialization... The Mask ROM will have already initialized
 240          * basic memory.  Go here to bump up clock rate and handle wake up conditions.
 241          */
 242         mov     ip, lr          /* persevere link reg across call */
 243         bl      lowlevel_init   /* go setup pll,mux,memory */
 244         mov     lr, ip          /* restore link */
 245         mov     pc, lr          /* back to my caller */
 246
 247 #ifndef CONFIG_ONENAND_IPL
 248 /*
 249  *************************************************************************
 250  *
 251  * Interrupt handling
 252  *
 253  *************************************************************************
 254  */
 255 @
 256 @ IRQ stack frame.
 257 @
 258 #define S_FRAME_SIZE    72
 259
 260 #define S_OLD_R0        68
 261 #define S_PSR           64
 262 #define S_PC            60
 263 #define S_LR            56
 264 #define S_SP            52
 265
 266 #define S_IP            48
 267 #define S_FP            44
 268 #define S_R10           40
 269 #define S_R9            36
 270 #define S_R8            32
 271 #define S_R7            28
 272 #define S_R6            24
 273 #define S_R5            20
 274 #define S_R4            16
 275 #define S_R3            12
 276 #define S_R2            8
 277 #define S_R1            4
 278 #define S_R0            0
 279
 280 #define MODE_SVC 0x13
 281 #define I_BIT    0x80
 282
 283 /*
 284  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 285  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 286  */
 287
 288         .macro  bad_save_user_regs
 289         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 290         stmia   sp, {r0 - r12}                  @ Save user registers (now in svc mode) r0-r12
 291
 292         ldr     r2, _armboot_start
 293         sub     r2, r2, #(CONFIG_SYS_MALLOC_LEN)
 294         sub     r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)   @ set base 2 words into abort stack
 295         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 296         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 297
 298         add     r5, sp, #S_SP
 299         mov     r1, lr
 300         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 301         mov     r0, sp                          @ save current stack into r0 (param register)
 302         .endm
 303
 304         .macro  irq_save_user_regs
 305         sub     sp, sp, #S_FRAME_SIZE
 306         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 307         add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 308         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 309         str     lr, [r8, #0]                    @ Save calling PC
 310         mrs     r6, spsr
 311         str     r6, [r8, #4]                    @ Save CPSR
 312         str     r0, [r8, #8]                    @ Save OLD_R0
 313         mov     r0, sp
 314         .endm
 315
 316         .macro  irq_restore_user_regs
 317         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 318         mov     r0, r0
 319         ldr     lr, [sp, #S_PC]                 @ Get PC
 320         add     sp, sp, #S_FRAME_SIZE
 321         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 322         .endm
 323
 324         .macro get_bad_stack
 325         ldr     r13, _armboot_start             @ setup our mode stack (enter in banked mode)
 326         sub     r13, r13, #(CONFIG_SYS_MALLOC_LEN)      @ move past malloc pool
 327         sub     r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
 328
 329         str     lr, [r13]                       @ save caller lr in position 0 of saved stack
 330         mrs     lr, spsr                        @ get the spsr
 331         str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
 332
 333         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 334         @ msr   spsr_c, r13
 335         msr     spsr, r13                       @ switch modes, make sure moves will execute
 336         mov     lr, pc                          @ capture return pc
 337         movs    pc, lr                          @ jump to next instruction & switch modes.
 338         .endm
 339
 340         .macro get_bad_stack_swi
 341         sub     r13, r13, #4                    @ space on current stack for scratch reg.
 342         str     r0, [r13]                       @ save R0's value.
 343         ldr     r0, _armboot_start              @ get data regions start
 344         sub     r0, r0, #(CONFIG_SYS_MALLOC_LEN)        @ move past malloc pool
 345         sub     r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8)   @ move past gbl and a couple spots for abort stack
 346         str     lr, [r0]                        @ save caller lr in position 0 of saved stack
 347         mrs     r0, spsr                        @ get the spsr
 348         str     lr, [r0, #4]                    @ save spsr in position 1 of saved stack
 349         ldr     r0, [r13]                       @ restore r0
 350         add     r13, r13, #4                    @ pop stack entry
 351         .endm
 352
 353         .macro get_irq_stack                    @ setup IRQ stack
 354         ldr     sp, IRQ_STACK_START
 355         .endm
 356
 357         .macro get_fiq_stack                    @ setup FIQ stack
 358         ldr     sp, FIQ_STACK_START
 359         .endm
 360 #endif  /* CONFIG_ONENAND_IPL */
 361
 362 /*
 363  * exception handlers
 364  */
 365 #ifdef CONFIG_ONENAND_IPL
 366         .align  5
 367 do_hang:
 368         ldr     sp, _TEXT_BASE                  /* use 32 words about stack */
 369         bl      hang                            /* hang and never return */
 370 #else   /* !CONFIG_ONENAND IPL */
 371         .align  5
 372 undefined_instruction:
 373         get_bad_stack
 374         bad_save_user_regs
 375         bl      do_undefined_instruction
 376
 377         .align  5
 378 software_interrupt:
 379         get_bad_stack_swi
 380         bad_save_user_regs
 381         bl      do_software_interrupt
 382
 383         .align  5
 384 prefetch_abort:
 385         get_bad_stack
 386         bad_save_user_regs
 387         bl      do_prefetch_abort
 388
 389         .align  5
 390 data_abort:
 391         get_bad_stack
 392         bad_save_user_regs
 393         bl      do_data_abort
 394
 395         .align  5
 396 not_used:
 397         get_bad_stack
 398         bad_save_user_regs
 399         bl      do_not_used
 400
 401 #ifdef CONFIG_USE_IRQ
 402
 403         .align  5
 404 irq:
 405         get_irq_stack
 406         irq_save_user_regs
 407         bl      do_irq
 408         irq_restore_user_regs
 409
 410         .align  5
 411 fiq:
 412         get_fiq_stack
 413         /* someone ought to write a more effiction fiq_save_user_regs */
 414         irq_save_user_regs
 415         bl      do_fiq
 416         irq_restore_user_regs
 417
 418 #else
 419
 420         .align  5
 421 irq:
 422         get_bad_stack
 423         bad_save_user_regs
 424         bl      do_irq
 425
 426         .align  5
 427 fiq:
 428         get_bad_stack
 429         bad_save_user_regs
 430         bl      do_fiq
 431
 432 #endif
 433         .align 5
 434 .global arm1136_cache_flush
 435 arm1136_cache_flush:
 436                 mcr     p15, 0, r1, c7, c5, 0   @ invalidate I cache
 437                 mov     pc, lr                  @ back to caller
 438 #endif  /* CONFIG_ONENAND_IPL */