cpu/arm720t/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Alex Zuepke <azu@sysgo.de>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * CPU specific code
  31  */
  32
  33 #include <common.h>
  34 #include <command.h>
  35 #include <clps7111.h>
  36 #include <asm/hardware.h>
  37
  38 int cpu_init (void)
  39 {
  40         /*
  41          * setup up stacks if necessary
  42          */
  43 #ifdef CONFIG_USE_IRQ
  44         IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
  45         FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  46 #endif
  47         return 0;
  48 }
  49
  50 int cleanup_before_linux (void)
  51 {
  52         /*
  53          * this function is called just before we call linux
  54          * it prepares the processor for linux
  55          *
  56          * we turn off caches etc ...
  57          * and we set the CPU-speed to 73 MHz - see start.S for details
  58          */
  59
  60 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
  61         unsigned long i;
  62
  63         disable_interrupts ();
  64
  65         /* turn off I-cache */
  66         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  67         i &= ~0x1000;
  68         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
  69
  70         /* flush I-cache */
  71         asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
  72 #ifdef CONFIG_ARM7_REVD
  73         /* go to high speed */
  74         IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
  75 #endif
  76 #elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
  77         disable_interrupts ();
  78         /* Nothing more needed */
  79 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
  80         /* No cleanup before linux for IntegratorAP/CM720T as yet */
  81 #else
  82 #error No cleanup_before_linux() defined for this CPU type
  83 #endif
  84         return 0;
  85 }
  86
  87 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  88 {
  89         disable_interrupts ();
  90         reset_cpu (0);
  91         /*NOTREACHED*/
  92         return (0);
  93 }
  94
  95 /*
  96  * Instruction and Data cache enable and disable functions
  97  *
  98  */
  99
 100 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
 101 /* read co-processor 15, register #1 (control register) */
 102 static unsigned long read_p15_c1(void)
 103 {
 104         unsigned long value;
 105
 106         __asm__ __volatile__(
 107                 "mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
 108                 : "=r" (value)
 109                 :
 110                 : "memory");
 111         /* printf("p15/c1 is = %08lx\n", value); */
 112         return value;
 113 }
 114
 115 /* write to co-processor 15, register #1 (control register) */
 116 static void write_p15_c1(unsigned long value)
 117 {
 118         /* printf("write %08lx to p15/c1\n", value); */
 119         __asm__ __volatile__(
 120                 "mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
 121                 :
 122                 : "r" (value)
 123                 : "memory");
 124
 125         read_p15_c1();
 126 }
 127
 128 static void cp_delay (void)
 129 {
 130         volatile int i;
 131
 132         /* copro seems to need some delay between reading and writing */
 133         for (i = 0; i < 100; i++);
 134 }
 135
 136 /* See also ARM Ref. Man. */
 137 #define C1_MMU          (1<<0)  /* mmu off/on */
 138 #define C1_ALIGN        (1<<1)  /* alignment faults off/on */
 139 #define C1_IDC          (1<<2)  /* icache and/or dcache off/on */
 140 #define C1_WRITE_BUFFER (1<<3)  /* write buffer off/on */
 141 #define C1_BIG_ENDIAN   (1<<7)  /* big endian off/on */
 142 #define C1_SYS_PROT     (1<<8)  /* system protection */
 143 #define C1_ROM_PROT     (1<<9)  /* ROM protection */
 144 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
 145
 146 void icache_enable (void)
 147 {
 148         ulong reg;
 149
 150         reg = read_p15_c1 ();
 151         cp_delay ();
 152         write_p15_c1 (reg | C1_IDC);
 153 }
 154
 155 void icache_disable (void)
 156 {
 157         ulong reg;
 158
 159         reg = read_p15_c1 ();
 160         cp_delay ();
 161         write_p15_c1 (reg & ~C1_IDC);
 162 }
 163
 164 int icache_status (void)
 165 {
 166         return (read_p15_c1 () & C1_IDC) != 0;
 167 }
 168
 169 void dcache_enable (void)
 170 {
 171         ulong reg;
 172
 173         reg = read_p15_c1 ();
 174         cp_delay ();
 175         write_p15_c1 (reg | C1_IDC);
 176 }
 177
 178 void dcache_disable (void)
 179 {
 180         ulong reg;
 181
 182         reg = read_p15_c1 ();
 183         cp_delay ();
 184         write_p15_c1 (reg & ~C1_IDC);
 185 }
 186
 187 int dcache_status (void)
 188 {
 189         return (read_p15_c1 () & C1_IDC) != 0;
 190 }
 191
 192 #elif defined(CONFIG_S3C4510B)
 193
 194 void icache_enable (void)
 195 {
 196         s32 i;
 197
 198         /* disable all cache bits */
 199         CLR_REG( REG_SYSCFG, 0x3F);
 200
 201         /* 8KB cache, write enable */
 202         SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
 203
 204         /* clear TAG RAM bits */
 205         for ( i = 0; i < 256; i++)
 206           PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
 207
 208         /* clear SET0 RAM */
 209         for(i=0; i < 1024; i++)
 210           PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
 211
 212         /* clear SET1 RAM */
 213         for(i=0; i < 1024; i++)
 214           PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
 215
 216         /* enable cache */
 217         SET_REG( REG_SYSCFG, CACHE_ENABLE);
 218
 219 }
 220
 221 void icache_disable (void)
 222 {
 223         /* disable all cache bits */
 224         CLR_REG( REG_SYSCFG, 0x3F);
 225 }
 226
 227 int icache_status (void)
 228 {
 229         return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
 230 }
 231
 232 void dcache_enable (void)
 233 {
 234         /* we don't have seperate instruction/data caches */
 235         icache_enable();
 236 }
 237
 238 void dcache_disable (void)
 239 {
 240         /* we don't have seperate instruction/data caches */
 241         icache_disable();
 242 }
 243
 244 int dcache_status (void)
 245 {
 246         /* we don't have seperate instruction/data caches */
 247         return icache_status();
 248 }
 249
 250 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 251         /* No specific cache setup for IntegratorAP/CM720T as yet */
 252         void icache_enable (void)
 253         {
 254         }
 255 #elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
 256 #else
 257 #error No icache/dcache enable/disable functions defined for this CPU type
 258 #endif