cpu/arm920t/ep93xx/lowlevel_init.S

   1 /*
   2  * Low-level initialization for EP93xx
   3  *
   4  * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
   5  *
   6  * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <version.h>
  28 #include <asm/arch/ep93xx.h>
  29
  30 .globl lowlevel_init
  31 lowlevel_init:
  32         /* backup return address */
  33         ldr r1, =SYSCON_SCRATCH0
  34         str lr, [r1]
  35
  36         /* Turn on both LEDs */
  37         bl red_LED_on
  38         bl green_LED_on
  39
  40         /* Configure flash wait states before we switch to the PLL */
  41         bl flash_cfg
  42
  43         /* Set up PLL */
  44         bl pll_cfg
  45
  46         /* Turn off the Green LED and leave the Red LED on */
  47         bl green_LED_off
  48
  49         /* Setup SDRAM */
  50         bl sdram_cfg
  51
  52         /* Turn on Green LED, Turn off the Red LED */
  53         bl green_LED_on
  54         bl red_LED_off
  55
  56         /* FIXME: we use async mode for now */
  57         mrc p15, 0, r0, c1, c0, 0
  58         orr r0, r0, #0xc0000000
  59         mcr p15, 0, r0, c1, c0, 0
  60
  61         /* restore return address */
  62         ldr r1, =SYSCON_SCRATCH0
  63         ldr lr, [r1]
  64
  65         mov pc, lr