cpu/arm925t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM925 CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1510 from ARM920 code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <gj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij          <kshitij@ti.com>
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33
  34
  35 #include <config.h>
  36 #include <version.h>
  37
  38 #if defined(CONFIG_OMAP1510)
  39 #include <./configs/omap1510.h>
  40 #endif
  41
  42 /*
  43  *************************************************************************
  44  *
  45  * Jump vector table as in table 3.1 in [1]
  46  *
  47  *************************************************************************
  48  */
  49
  50
  51 .globl _start
  52 _start: b       reset
  53         ldr     pc, _undefined_instruction
  54         ldr     pc, _software_interrupt
  55         ldr     pc, _prefetch_abort
  56         ldr     pc, _data_abort
  57         ldr     pc, _not_used
  58         ldr     pc, _irq
  59         ldr     pc, _fiq
  60
  61 _undefined_instruction: .word undefined_instruction
  62 _software_interrupt:    .word software_interrupt
  63 _prefetch_abort:        .word prefetch_abort
  64 _data_abort:            .word data_abort
  65 _not_used:              .word not_used
  66 _irq:                   .word irq
  67 _fiq:                   .word fiq
  68
  69         .balignl 16,0xdeadbeef
  70
  71
  72 /*
  73  *************************************************************************
  74  *
  75  * Startup Code (reset vector)
  76  *
  77  * do important init only if we don't start from memory!
  78  * setup Memory and board specific bits prior to relocation.
  79  * relocate armboot to ram
  80  * setup stack
  81  *
  82  *************************************************************************
  83  */
  84
  85 /*
  86  * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  87  */
  88 _TEXT_BASE:
  89         .word   TEXT_BASE
  90
  91 .globl _armboot_start
  92 _armboot_start:
  93         .word _start
  94
  95 /*
  96  * Note: _armboot_end_data and _armboot_end are defined
  97  * by the (board-dependent) linker script.
  98  * _armboot_end_data is the first usable FLASH address after armboot
  99  */
 100 .globl _armboot_end_data
 101 _armboot_end_data:
 102         .word armboot_end_data
 103 .globl _armboot_end
 104 _armboot_end:
 105         .word armboot_end
 106
 107 /*
 108  * _armboot_real_end is the first usable RAM address behind armboot
 109  * and the various stacks
 110  */
 111 .globl _armboot_real_end
 112 _armboot_real_end:
 113         .word 0x0badc0de
 114
 115 #ifdef CONFIG_USE_IRQ
 116 /* IRQ stack memory (calculated at run-time) */
 117 .globl IRQ_STACK_START
 118 IRQ_STACK_START:
 119         .word   0x0badc0de
 120
 121 /* IRQ stack memory (calculated at run-time) */
 122 .globl FIQ_STACK_START
 123 FIQ_STACK_START:
 124         .word 0x0badc0de
 125 #endif
 126
 127
 128 /*
 129  * the actual reset code
 130  */
 131
 132 reset:
 133         /*
 134          * set the cpu to SVC32 mode
 135          */
 136         mrs     r0,cpsr
 137         bic     r0,r0,#0x1f
 138         orr     r0,r0,#0xd3
 139         msr     cpsr,r0
 140
 141         /*
 142          * Set up 925T mode
 143          */
 144         mov r1, #0x81               /* Set ARM925T configuration. */
 145         mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
 146
 147         /*
 148          * turn off the watchdog, unlock/diable sequence
 149          */
 150         mov  r1, #0xF5
 151         ldr  r0, =WDTIM_MODE
 152         strh r1, [r0]
 153         mov  r1, #0xA0
 154         strh r1, [r0]
 155
 156         /*
 157          * mask all IRQs by setting all bits in the INTMR - default
 158          */
 159         mov r1, #0xffffffff
 160         ldr r0, =REG_IHL1_MIR
 161         str r1, [r0]
 162         ldr r0, =REG_IHL2_MIR
 163         str r1, [r0]
 164
 165         /*
 166          * wait for dpll to lock
 167          */
 168         ldr  r0, =CK_DPLL1
 169         mov  r1, #0x10
 170         strh r1, [r0]
 171 poll1:
 172         ldrh r1, [r0]
 173         ands r1, r1, #0x01
 174         beq poll1
 175         bl  cpu_init_crit
 176
 177 relocate:
 178         /*
 179          * relocate armboot to RAM
 180          */
 181         adr     r0, _start              /* r0 <- current position of code */
 182         ldr     r2, _armboot_start
 183         ldr     r3, _armboot_end
 184         sub     r2, r3, r2              /* r2 <- size of armboot */
 185         ldr     r1, _TEXT_BASE          /* r1 <- destination address */
 186         add     r2, r0, r2              /* r2 <- source end address */
 187
 188         /*
 189          * r0 = source address
 190          * r1 = target address
 191          * r2 = source end address
 192          */
 193 copy_loop:
 194         ldmia   r0!, {r3-r10}
 195         stmia   r1!, {r3-r10}
 196         cmp     r0, r2
 197         ble     copy_loop
 198
 199         /* set up the stack */
 200         ldr     r0, _armboot_end
 201         add     r0, r0, #CONFIG_STACKSIZE
 202         sub     sp, r0, #12             /* leave 3 words for abort-stack */
 203
 204         ldr     pc, _start_armboot
 205
 206 _start_armboot: .word start_armboot
 207
 208
 209 /*
 210  *************************************************************************
 211  *
 212  * CPU_init_critical registers
 213  *
 214  * setup important registers
 215  * setup memory timing
 216  *
 217  *************************************************************************
 218  */
 219
 220
 221 cpu_init_crit:
 222         /*
 223          * flush v4 I/D caches
 224          */
 225         mov     r0, #0
 226         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 227         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 228
 229         /*
 230          * disable MMU stuff and caches
 231          */
 232         mrc     p15, 0, r0, c1, c0, 0
 233         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 234         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 235         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 236         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 237         mcr     p15, 0, r0, c1, c0, 0
 238
 239         /*
 240          * Go setup Memory and board specific bits prior to relocation.
 241          */
 242         mov     ip, lr          /* perserve link reg across call */
 243         bl      platformsetup   /* go setup pll,mux,memory */
 244         mov     lr, ip          /* restore link */
 245         mov     pc, lr          /* back to my caller */
 246 /*
 247  *************************************************************************
 248  *
 249  * Interrupt handling
 250  *
 251  *************************************************************************
 252  */
 253
 254 @
 255 @ IRQ stack frame.
 256 @
 257 #define S_FRAME_SIZE    72
 258
 259 #define S_OLD_R0        68
 260 #define S_PSR           64
 261 #define S_PC            60
 262 #define S_LR            56
 263 #define S_SP            52
 264
 265 #define S_IP            48
 266 #define S_FP            44
 267 #define S_R10           40
 268 #define S_R9            36
 269 #define S_R8            32
 270 #define S_R7            28
 271 #define S_R6            24
 272 #define S_R5            20
 273 #define S_R4            16
 274 #define S_R3            12
 275 #define S_R2            8
 276 #define S_R1            4
 277 #define S_R0            0
 278
 279 #define MODE_SVC 0x13
 280 #define I_BIT    0x80
 281
 282 /*
 283  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 284  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 285  */
 286
 287         .macro  bad_save_user_regs
 288         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 289         stmia   sp, {r0 - r12}                  @ Save user registers (now in svc mode) r0-r12
 290
 291         ldr     r2, _armboot_end                @ find top of stack
 292         add     r2, r2, #CONFIG_STACKSIZE       @ find base of normal stack
 293         sub     r2, r2, #8                      @ set base 2 words into abort stack
 294         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 295         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 296
 297         add     r5, sp, #S_SP
 298         mov     r1, lr
 299         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 300         mov     r0, sp                          @ save current stack into r0 (param register)
 301         .endm
 302
 303         .macro  irq_save_user_regs
 304         sub     sp, sp, #S_FRAME_SIZE
 305         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 306         add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 307         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 308         str     lr, [r8, #0]                    @ Save calling PC
 309         mrs     r6, spsr
 310         str     r6, [r8, #4]                    @ Save CPSR
 311         str     r0, [r8, #8]                    @ Save OLD_R0
 312         mov     r0, sp
 313         .endm
 314
 315         .macro  irq_restore_user_regs
 316         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 317         mov     r0, r0
 318         ldr     lr, [sp, #S_PC]                 @ Get PC
 319         add     sp, sp, #S_FRAME_SIZE
 320         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 321         .endm
 322
 323         .macro get_bad_stack
 324         ldr     r13, _armboot_end               @ get bottom of stack (into sp by by user stack pointer).
 325         add     r13, r13, #CONFIG_STACKSIZE     @ head to reserved words at the top of the stack
 326         sub     r13, r13, #8                    @ reserved a couple spots in abort stack
 327
 328         str     lr, [r13]                       @ save caller lr in position 0 of saved stack
 329         mrs     lr, spsr                        @ get the spsr
 330         str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
 331
 332         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 333         @ msr   spsr_c, r13
 334         msr     spsr, r13                       @ switch modes, make sure moves will execute
 335         mov     lr, pc                          @ capture return pc
 336         movs    pc, lr                          @ jump to next instruction & switch modes.
 337         .endm
 338
 339         .macro get_irq_stack                    @ setup IRQ stack
 340         ldr     sp, IRQ_STACK_START
 341         .endm
 342
 343         .macro get_fiq_stack                    @ setup FIQ stack
 344         ldr     sp, FIQ_STACK_START
 345         .endm
 346
 347 /*
 348  * exception handlers
 349  */
 350         .align  5
 351 undefined_instruction:
 352         get_bad_stack
 353         bad_save_user_regs
 354         bl      do_undefined_instruction
 355
 356         .align  5
 357 software_interrupt:
 358         get_bad_stack
 359         bad_save_user_regs
 360         bl      do_software_interrupt
 361
 362         .align  5
 363 prefetch_abort:
 364         get_bad_stack
 365         bad_save_user_regs
 366         bl      do_prefetch_abort
 367
 368         .align  5
 369 data_abort:
 370         get_bad_stack
 371         bad_save_user_regs
 372         bl      do_data_abort
 373
 374         .align  5
 375 not_used:
 376         get_bad_stack
 377         bad_save_user_regs
 378         bl      do_not_used
 379
 380 #ifdef CONFIG_USE_IRQ
 381
 382         .align  5
 383 irq:
 384         get_irq_stack
 385         irq_save_user_regs
 386         bl      do_irq
 387         irq_restore_user_regs
 388
 389         .align  5
 390 fiq:
 391         get_fiq_stack
 392         /* someone ought to write a more effiction fiq_save_user_regs */
 393         irq_save_user_regs
 394         bl      do_fiq
 395         irq_restore_user_regs
 396
 397 #else
 398
 399         .align  5
 400 irq:
 401         get_bad_stack
 402         bad_save_user_regs
 403         bl      do_irq
 404
 405         .align  5
 406 fiq:
 407         get_bad_stack
 408         bad_save_user_regs
 409         bl      do_fiq
 410
 411 #endif
 412
 413         .align  5
 414 .globl reset_cpu
 415 reset_cpu:
 416         ldr     r1, rstctl1     /* get clkm1 reset ctl */
 417         mov     r3, #0x0
 418         strh    r3, [r1]        /* clear it */
 419         mov     r3, #0x8
 420         strh    r3, [r1]        /* force dsp+arm reset */
 421 _loop_forever:
 422         b       _loop_forever
 423 rstctl1:
 424         .word   0xfffece10