cpu/arm925t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM925 CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1510 from ARM920 code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <gj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij          <kshitij@ti.com>
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33
  34 #include <config.h>
  35 #include <version.h>
  36
  37 #if defined(CONFIG_OMAP1510)
  38 #include <./configs/omap1510.h>
  39 #endif
  40
  41 /*
  42  *************************************************************************
  43  *
  44  * Jump vector table as in table 3.1 in [1]
  45  *
  46  *************************************************************************
  47  */
  48
  49
  50 .globl _start
  51 _start: b       reset
  52         ldr     pc, _undefined_instruction
  53         ldr     pc, _software_interrupt
  54         ldr     pc, _prefetch_abort
  55         ldr     pc, _data_abort
  56         ldr     pc, _not_used
  57         ldr     pc, _irq
  58         ldr     pc, _fiq
  59
  60 _undefined_instruction: .word undefined_instruction
  61 _software_interrupt:    .word software_interrupt
  62 _prefetch_abort:        .word prefetch_abort
  63 _data_abort:            .word data_abort
  64 _not_used:              .word not_used
  65 _irq:                   .word irq
  66 _fiq:                   .word fiq
  67
  68         .balignl 16,0xdeadbeef
  69
  70
  71 /*
  72  *************************************************************************
  73  *
  74  * Startup Code (reset vector)
  75  *
  76  * do important init only if we don't start from memory!
  77  * setup Memory and board specific bits prior to relocation.
  78  * relocate armboot to ram
  79  * setup stack
  80  *
  81  *************************************************************************
  82  */
  83
  84 /*
  85  * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  86  */
  87 _TEXT_BASE:
  88         .word   TEXT_BASE
  89
  90 .globl _armboot_start
  91 _armboot_start:
  92         .word _start
  93
  94 /*
  95  * Note: _armboot_end_data and _armboot_end are defined
  96  * by the (board-dependent) linker script.
  97  * _armboot_end_data is the first usable FLASH address after armboot
  98  */
  99 .globl _armboot_end_data
 100 _armboot_end_data:
 101         .word armboot_end_data
 102 .globl _armboot_end
 103 _armboot_end:
 104         .word armboot_end
 105
 106 /*
 107  * _armboot_real_end is the first usable RAM address behind armboot
 108  * and the various stacks
 109  */
 110 .globl _armboot_real_end
 111 _armboot_real_end:
 112         .word 0x0badc0de
 113
 114 #ifdef CONFIG_USE_IRQ
 115 /* IRQ stack memory (calculated at run-time) */
 116 .globl IRQ_STACK_START
 117 IRQ_STACK_START:
 118         .word   0x0badc0de
 119
 120 /* IRQ stack memory (calculated at run-time) */
 121 .globl FIQ_STACK_START
 122 FIQ_STACK_START:
 123         .word 0x0badc0de
 124 #endif
 125
 126
 127 /*
 128  * the actual reset code
 129  */
 130
 131 reset:
 132         /*
 133          * set the cpu to SVC32 mode
 134          */
 135         mrs     r0,cpsr
 136         bic     r0,r0,#0x1f
 137         orr     r0,r0,#0xd3
 138         msr     cpsr,r0
 139
 140         /*
 141          * Set up 925T mode
 142          */
 143         mov r1, #0x81               /* Set ARM925T configuration. */
 144         mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
 145
 146         /*
 147          * turn off the watchdog, unlock/diable sequence
 148          */
 149         mov  r1, #0xF5
 150         ldr  r0, =WDTIM_MODE
 151         strh r1, [r0]
 152         mov  r1, #0xA0
 153         strh r1, [r0]
 154
 155         /*
 156          * mask all IRQs by setting all bits in the INTMR - default
 157          */
 158         mov r1, #0xffffffff
 159         ldr r0, =REG_IHL1_MIR
 160         str r1, [r0]
 161         ldr r0, =REG_IHL2_MIR
 162         str r1, [r0]
 163
 164         /*
 165          * wait for dpll to lock
 166          */
 167         ldr  r0, =CK_DPLL1
 168         mov  r1, #0x10
 169         strh r1, [r0]
 170 poll1:
 171         ldrh r1, [r0]
 172         ands r1, r1, #0x01
 173         beq poll1
 174         bl  cpu_init_crit
 175
 176 relocate:
 177         /*
 178          * relocate armboot to RAM
 179          */
 180         adr     r0, _start              /* r0 <- current position of code */
 181         ldr     r2, _armboot_start
 182         ldr     r3, _armboot_end
 183         sub     r2, r3, r2              /* r2 <- size of armboot */
 184         ldr     r1, _TEXT_BASE          /* r1 <- destination address */
 185         add     r2, r0, r2              /* r2 <- source end address */
 186
 187         /*
 188          * r0 = source address
 189          * r1 = target address
 190          * r2 = source end address
 191          */
 192 copy_loop:
 193         ldmia   r0!, {r3-r10}
 194         stmia   r1!, {r3-r10}
 195         cmp     r0, r2
 196         ble     copy_loop
 197
 198         /* set up the stack */
 199         ldr     r0, _armboot_end
 200         add     r0, r0, #CONFIG_STACKSIZE
 201         sub     sp, r0, #12             /* leave 3 words for abort-stack */
 202
 203         ldr     pc, _start_armboot
 204
 205 _start_armboot: .word start_armboot
 206
 207
 208 /*
 209  *************************************************************************
 210  *
 211  * CPU_init_critical registers
 212  *
 213  * setup important registers
 214  * setup memory timing
 215  *
 216  *************************************************************************
 217  */
 218
 219
 220 cpu_init_crit:
 221         /*
 222          * flush v4 I/D caches
 223          */
 224         mov     r0, #0
 225         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 226         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 227
 228         /*
 229          * disable MMU stuff and caches
 230          */
 231         mrc     p15, 0, r0, c1, c0, 0
 232         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 233         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 234         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 235         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 236         mcr     p15, 0, r0, c1, c0, 0
 237
 238         /*
 239          * Go setup Memory and board specific bits prior to relocation.
 240          */
 241         mov     ip, lr          /* perserve link reg across call */
 242         bl      platformsetup   /* go setup pll,mux,memory */
 243         mov     lr, ip          /* restore link */
 244         mov     pc, lr          /* back to my caller */
 245 /*
 246  *************************************************************************
 247  *
 248  * Interrupt handling
 249  *
 250  *************************************************************************
 251  */
 252
 253 @
 254 @ IRQ stack frame.
 255 @
 256 #define S_FRAME_SIZE    72
 257
 258 #define S_OLD_R0        68
 259 #define S_PSR           64
 260 #define S_PC            60
 261 #define S_LR            56
 262 #define S_SP            52
 263
 264 #define S_IP            48
 265 #define S_FP            44
 266 #define S_R10           40
 267 #define S_R9            36
 268 #define S_R8            32
 269 #define S_R7            28
 270 #define S_R6            24
 271 #define S_R5            20
 272 #define S_R4            16
 273 #define S_R3            12
 274 #define S_R2            8
 275 #define S_R1            4
 276 #define S_R0            0
 277
 278 #define MODE_SVC 0x13
 279 #define I_BIT    0x80
 280
 281 /*
 282  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 283  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 284  */
 285
 286         .macro  bad_save_user_regs
 287         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 288         stmia   sp, {r0 - r12}                  @ Save user registers (now in svc mode) r0-r12
 289
 290         ldr     r2, _armboot_end                @ find top of stack
 291         add     r2, r2, #CONFIG_STACKSIZE       @ find base of normal stack
 292         sub     r2, r2, #8                      @ set base 2 words into abort stack
 293         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 294         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 295
 296         add     r5, sp, #S_SP
 297         mov     r1, lr
 298         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 299         mov     r0, sp                          @ save current stack into r0 (param register)
 300         .endm
 301
 302         .macro  irq_save_user_regs
 303         sub     sp, sp, #S_FRAME_SIZE
 304         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 305         add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 306         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 307         str     lr, [r8, #0]                    @ Save calling PC
 308         mrs     r6, spsr
 309         str     r6, [r8, #4]                    @ Save CPSR
 310         str     r0, [r8, #8]                    @ Save OLD_R0
 311         mov     r0, sp
 312         .endm
 313
 314         .macro  irq_restore_user_regs
 315         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 316         mov     r0, r0
 317         ldr     lr, [sp, #S_PC]                 @ Get PC
 318         add     sp, sp, #S_FRAME_SIZE
 319         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 320         .endm
 321
 322         .macro get_bad_stack
 323         ldr     r13, _armboot_end               @ get bottom of stack (into sp by by user stack pointer).
 324         add     r13, r13, #CONFIG_STACKSIZE     @ head to reserved words at the top of the stack
 325         sub     r13, r13, #8                    @ reserved a couple spots in abort stack
 326
 327         str     lr, [r13]                       @ save caller lr in position 0 of saved stack
 328         mrs     lr, spsr                        @ get the spsr
 329         str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
 330
 331         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 332         @ msr   spsr_c, r13
 333         msr     spsr, r13                       @ switch modes, make sure moves will execute
 334         mov     lr, pc                          @ capture return pc
 335         movs    pc, lr                          @ jump to next instruction & switch modes.
 336         .endm
 337
 338         .macro get_irq_stack                    @ setup IRQ stack
 339         ldr     sp, IRQ_STACK_START
 340         .endm
 341
 342         .macro get_fiq_stack                    @ setup FIQ stack
 343         ldr     sp, FIQ_STACK_START
 344         .endm
 345
 346 /*
 347  * exception handlers
 348  */
 349         .align  5
 350 undefined_instruction:
 351         get_bad_stack
 352         bad_save_user_regs
 353         bl      do_undefined_instruction
 354
 355         .align  5
 356 software_interrupt:
 357         get_bad_stack
 358         bad_save_user_regs
 359         bl      do_software_interrupt
 360
 361         .align  5
 362 prefetch_abort:
 363         get_bad_stack
 364         bad_save_user_regs
 365         bl      do_prefetch_abort
 366
 367         .align  5
 368 data_abort:
 369         get_bad_stack
 370         bad_save_user_regs
 371         bl      do_data_abort
 372
 373         .align  5
 374 not_used:
 375         get_bad_stack
 376         bad_save_user_regs
 377         bl      do_not_used
 378
 379 #ifdef CONFIG_USE_IRQ
 380
 381         .align  5
 382 irq:
 383         get_irq_stack
 384         irq_save_user_regs
 385         bl      do_irq
 386         irq_restore_user_regs
 387
 388         .align  5
 389 fiq:
 390         get_fiq_stack
 391         /* someone ought to write a more effiction fiq_save_user_regs */
 392         irq_save_user_regs
 393         bl      do_fiq
 394         irq_restore_user_regs
 395
 396 #else
 397
 398         .align  5
 399 irq:
 400         get_bad_stack
 401         bad_save_user_regs
 402         bl      do_irq
 403
 404         .align  5
 405 fiq:
 406         get_bad_stack
 407         bad_save_user_regs
 408         bl      do_fiq
 409
 410 #endif
 411
 412         .align  5
 413 .globl reset_cpu
 414 reset_cpu:
 415         ldr     r1, rstctl1     /* get clkm1 reset ctl */
 416         mov     r3, #0x3        /* dsp_en + arm_rst = global reset */
 417         strh    r3, [r1]        /* force reset */
 418         mov     r0, r0
 419 _loop_forever:
 420         b       _loop_forever
 421 rstctl1:
 422         .word   0xfffece10