cpu/arm926ejs/at91/clock.c

   1 /*
   2  * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <config.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/io.h>
  17 #include <asm/arch/at91_pmc.h>
  18 #include <asm/arch/clk.h>
  19
  20 static unsigned long cpu_clk_rate_hz;
  21 static unsigned long main_clk_rate_hz;
  22 static unsigned long mck_rate_hz;
  23 static unsigned long plla_rate_hz;
  24 static unsigned long pllb_rate_hz;
  25 static u32 at91_pllb_usb_init;
  26
  27 unsigned long get_cpu_clk_rate(void)
  28 {
  29         return cpu_clk_rate_hz;
  30 }
  31
  32 unsigned long get_main_clk_rate(void)
  33 {
  34         return main_clk_rate_hz;
  35 }
  36
  37 unsigned long get_mck_clk_rate(void)
  38 {
  39         return mck_rate_hz;
  40 }
  41
  42 unsigned long get_plla_clk_rate(void)
  43 {
  44         return plla_rate_hz;
  45 }
  46
  47 unsigned long get_pllb_clk_rate(void)
  48 {
  49         return pllb_rate_hz;
  50 }
  51
  52 u32 get_pllb_init(void)
  53 {
  54         return at91_pllb_usb_init;
  55 }
  56
  57 static unsigned long at91_css_to_rate(unsigned long css)
  58 {
  59         switch (css) {
  60         case AT91_PMC_MCKR_CSS_SLOW:
  61                 return AT91_SLOW_CLOCK;
  62         case AT91_PMC_MCKR_CSS_MAIN:
  63                 return main_clk_rate_hz;
  64         case AT91_PMC_MCKR_CSS_PLLA:
  65                 return plla_rate_hz;
  66         case AT91_PMC_MCKR_CSS_PLLB:
  67                 return pllb_rate_hz;
  68         }
  69
  70         return 0;
  71 }
  72
  73 #ifdef CONFIG_USB_ATMEL
  74 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
  75 {
  76         unsigned i, div = 0, mul = 0, diff = 1 << 30;
  77         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
  78
  79         /* PLL output max 240 MHz (or 180 MHz per errata) */
  80         if (out_freq > 240000000)
  81                 goto fail;
  82
  83         for (i = 1; i < 256; i++) {
  84                 int diff1;
  85                 unsigned input, mul1;
  86
  87                 /*
  88                  * PLL input between 1MHz and 32MHz per spec, but lower
  89                  * frequences seem necessary in some cases so allow 100K.
  90                  * Warning: some newer products need 2MHz min.
  91                  */
  92                 input = main_freq / i;
  93 #if defined(CONFIG_AT91SAM9G20)
  94                 if (input < 2000000)
  95                         continue;
  96 #endif
  97                 if (input < 100000)
  98                         continue;
  99                 if (input > 32000000)
 100                         continue;
 101
 102                 mul1 = out_freq / input;
 103 #if defined(CONFIG_AT91SAM9G20)
 104                 if (mul > 63)
 105                         continue;
 106 #endif
 107                 if (mul1 > 2048)
 108                         continue;
 109                 if (mul1 < 2)
 110                         goto fail;
 111
 112                 diff1 = out_freq - input * mul1;
 113                 if (diff1 < 0)
 114                         diff1 = -diff1;
 115                 if (diff > diff1) {
 116                         diff = diff1;
 117                         div = i;
 118                         mul = mul1;
 119                         if (diff == 0)
 120                                 break;
 121                 }
 122         }
 123         if (i == 256 && diff > (out_freq >> 5))
 124                 goto fail;
 125         return ret | ((mul - 1) << 16) | div;
 126 fail:
 127         return 0;
 128 }
 129 #endif
 130
 131 static u32 at91_pll_rate(u32 freq, u32 reg)
 132 {
 133         unsigned mul, div;
 134
 135         div = reg & 0xff;
 136         mul = (reg >> 16) & 0x7ff;
 137         if (div && mul) {
 138                 freq /= div;
 139                 freq *= mul + 1;
 140         } else
 141                 freq = 0;
 142
 143         return freq;
 144 }
 145
 146 int at91_clock_init(unsigned long main_clock)
 147 {
 148         unsigned freq, mckr;
 149         at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
 150 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
 151         unsigned tmp;
 152         /*
 153          * When the bootloader initialized the main oscillator correctly,
 154          * there's no problem using the cycle counter.  But if it didn't,
 155          * or when using oscillator bypass mode, we must be told the speed
 156          * of the main clock.
 157          */
 158         if (!main_clock) {
 159                 do {
 160                         tmp = readl(&pmc->mcfr);
 161                 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 162                 tmp &= AT91_PMC_MCFR_MAINF_MASK;
 163                 main_clock = tmp * (AT91_SLOW_CLOCK / 16);
 164         }
 165 #endif
 166         main_clk_rate_hz = main_clock;
 167
 168         /* report if PLLA is more than mildly overclocked */
 169         plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 170
 171 #ifdef CONFIG_USB_ATMEL
 172         /*
 173          * USB clock init:  choose 48 MHz PLLB value,
 174          * disable 48MHz clock during usb peripheral suspend.
 175          *
 176          * REVISIT:  assumes MCK doesn't derive from PLLB!
 177          */
 178         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 179                              AT91_PMC_PLLBR_USBDIV_2;
 180         pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
 181 #endif
 182
 183         /*
 184          * MCK and CPU derive from one of those primary clocks.
 185          * For now, assume this parentage won't change.
 186          */
 187         mckr = readl(&pmc->mckr);
 188 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 189         /* plla divisor by 2 */
 190         plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 191 #endif
 192         mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
 193         freq = mck_rate_hz;
 194
 195         freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
 196 #if defined(CONFIG_AT91RM9200)
 197         /* mdiv */
 198         mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 199 #elif defined(CONFIG_AT91SAM9G20)
 200         /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
 201         mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
 202                 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
 203         if (mckr & AT91_PMC_MCKR_MDIV_MASK)
 204                 freq /= 2;                      /* processor clock division */
 205 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 206         mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3
 207                 ? freq / 3
 208                 : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 209 #else
 210         mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 211 #endif
 212         cpu_clk_rate_hz = freq;
 213
 214         return 0;
 215 }