cpu/arm926ejs/davinci/cpu.c

   1 /*
   2  * Copyright (C) 2004 Texas Instruments.
   3  * Copyright (C) 2009 David Brownell
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <common.h>
  24 #include <netdev.h>
  25 #include <asm/arch/hardware.h>
  26
  27
  28 /* offsets from PLL controller base */
  29 #define PLLC_PLLCTL     0x100
  30 #define PLLC_PLLM       0x110
  31 #define PLLC_PREDIV     0x114
  32 #define PLLC_PLLDIV1    0x118
  33 #define PLLC_PLLDIV2    0x11c
  34 #define PLLC_PLLDIV3    0x120
  35 #define PLLC_POSTDIV    0x128
  36 #define PLLC_BPDIV      0x12c
  37 #define PLLC_PLLDIV4    0x160
  38 #define PLLC_PLLDIV5    0x164
  39 #define PLLC_PLLDIV6    0x168
  40 #define PLLC_PLLDIV8    0x170
  41 #define PLLC_PLLDIV9    0x174
  42
  43 #define BIT(x)          (1 << (x))
  44
  45 /* SOC-specific pll info */
  46 #ifdef CONFIG_SOC_DM355
  47 #define ARM_PLLDIV      PLLC_PLLDIV1
  48 #define DDR_PLLDIV      PLLC_PLLDIV1
  49 #endif
  50
  51 #ifdef CONFIG_SOC_DM644X
  52 #define ARM_PLLDIV      PLLC_PLLDIV2
  53 #define DSP_PLLDIV      PLLC_PLLDIV1
  54 #define DDR_PLLDIV      PLLC_PLLDIV2
  55 #endif
  56
  57 #ifdef CONFIG_SOC_DM6447
  58 #define ARM_PLLDIV      PLLC_PLLDIV2
  59 #define DSP_PLLDIV      PLLC_PLLDIV1
  60 #define DDR_PLLDIV      PLLC_PLLDIV1
  61 #endif
  62
  63
  64 #ifdef CONFIG_DISPLAY_CPUINFO
  65
  66 static unsigned pll_div(volatile void *pllbase, unsigned offset)
  67 {
  68         u32     div;
  69
  70         div = REG(pllbase + offset);
  71         return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
  72 }
  73
  74 static inline unsigned pll_prediv(volatile void *pllbase)
  75 {
  76 #ifdef CONFIG_SOC_DM355
  77         /* this register read seems to fail on pll0 */
  78         if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
  79                 return 8;
  80         else
  81                 return pll_div(pllbase, PLLC_PREDIV);
  82 #endif
  83         return 1;
  84 }
  85
  86 static inline unsigned pll_postdiv(volatile void *pllbase)
  87 {
  88 #ifdef CONFIG_SOC_DM355
  89         return pll_div(pllbase, PLLC_POSTDIV);
  90 #elif defined(CONFIG_SOC_DM6446)
  91         if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
  92                 return pll_div(pllbase, PLLC_POSTDIV);
  93 #endif
  94         return 1;
  95 }
  96
  97 static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
  98 {
  99         volatile void   *pllbase = (volatile void *) pll_addr;
 100         unsigned        base = CONFIG_SYS_HZ_CLOCK / 1000;
 101
 102         /* the PLL might be bypassed */
 103         if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
 104                 base /= pll_prediv(pllbase);
 105                 base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
 106                 base /= pll_postdiv(pllbase);
 107         }
 108         return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
 109 }
 110
 111 int print_cpuinfo(void)
 112 {
 113         /* REVISIT fetch and display CPU ID and revision information
 114          * too ... that will matter as more revisions appear.
 115          */
 116         printf("Cores: ARM %d MHz",
 117                         pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
 118
 119 #ifdef DSP_PLLDIV
 120         printf(", DSP %d MHz",
 121                         pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
 122 #endif
 123
 124         printf("\nDDR:   %d MHz\n",
 125                         /* DDR PHY uses an x2 input clock */
 126                         pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
 127                                 / 2);
 128         return 0;
 129 }
 130
 131 #endif
 132
 133 /*
 134  * Initializes on-chip ethernet controllers.
 135  * to override, implement board_eth_init()
 136  */
 137 int cpu_eth_init(bd_t *bis)
 138 {
 139 #if defined(CONFIG_DRIVER_TI_EMAC)
 140         davinci_emac_initialize();
 141 #endif
 142         return 0;
 143 }