cpu/arm926ejs/davinci/cpu.c

   1 /*
   2  * Copyright (C) 2004 Texas Instruments.
   3  * Copyright (C) 2009 David Brownell
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <common.h>
  24 #include <netdev.h>
  25 #include <asm/arch/hardware.h>
  26 #include <asm/io.h>
  27
  28 /* offsets from PLL controller base */
  29 #define PLLC_PLLCTL     0x100
  30 #define PLLC_PLLM       0x110
  31 #define PLLC_PREDIV     0x114
  32 #define PLLC_PLLDIV1    0x118
  33 #define PLLC_PLLDIV2    0x11c
  34 #define PLLC_PLLDIV3    0x120
  35 #define PLLC_POSTDIV    0x128
  36 #define PLLC_BPDIV      0x12c
  37 #define PLLC_PLLDIV4    0x160
  38 #define PLLC_PLLDIV5    0x164
  39 #define PLLC_PLLDIV6    0x168
  40 #define PLLC_PLLDIV8    0x170
  41 #define PLLC_PLLDIV9    0x174
  42
  43 #define BIT(x)          (1 << (x))
  44
  45 /* SOC-specific pll info */
  46 #ifdef CONFIG_SOC_DM355
  47 #define ARM_PLLDIV      PLLC_PLLDIV1
  48 #define DDR_PLLDIV      PLLC_PLLDIV1
  49 #endif
  50
  51 #ifdef CONFIG_SOC_DM644X
  52 #define ARM_PLLDIV      PLLC_PLLDIV2
  53 #define DSP_PLLDIV      PLLC_PLLDIV1
  54 #define DDR_PLLDIV      PLLC_PLLDIV2
  55 #endif
  56
  57 #ifdef CONFIG_SOC_DM6447
  58 #define ARM_PLLDIV      PLLC_PLLDIV2
  59 #define DSP_PLLDIV      PLLC_PLLDIV1
  60 #define DDR_PLLDIV      PLLC_PLLDIV1
  61 #endif
  62
  63 #ifdef CONFIG_SOC_DA8XX
  64 const dv_reg * const sysdiv[7] = {
  65         &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
  66         &davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
  67         &davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
  68         &davinci_pllc_regs->plldiv7
  69 };
  70
  71 int clk_get(enum davinci_clk_ids id)
  72 {
  73         int pre_div;
  74         int pllm;
  75         int post_div;
  76         int pll_out;
  77
  78         pll_out = CONFIG_SYS_OSCIN_FREQ;
  79
  80         if (id == DAVINCI_AUXCLK_CLKID)
  81                 goto out;
  82
  83         /*
  84          * Lets keep this simple. Combining operations can result in
  85          * unexpected approximations
  86          */
  87         pre_div = (readl(&davinci_pllc_regs->prediv) &
  88                    DAVINCI_PLLC_DIV_MASK) + 1;
  89         pllm = readl(&davinci_pllc_regs->pllm) + 1;
  90
  91         pll_out /= pre_div;
  92         pll_out *= pllm;
  93
  94         if (id == DAVINCI_PLLM_CLKID)
  95                 goto out;
  96
  97         post_div = (readl(&davinci_pllc_regs->postdiv) &
  98                     DAVINCI_PLLC_DIV_MASK) + 1;
  99
 100         pll_out /= post_div;
 101
 102         if (id == DAVINCI_PLLC_CLKID)
 103                 goto out;
 104
 105         pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
 106
 107 out:
 108         return pll_out;
 109 }
 110 #endif /* CONFIG_SOC_DA8XX */
 111
 112 #ifdef CONFIG_DISPLAY_CPUINFO
 113
 114 static unsigned pll_div(volatile void *pllbase, unsigned offset)
 115 {
 116         u32     div;
 117
 118         div = REG(pllbase + offset);
 119         return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
 120 }
 121
 122 static inline unsigned pll_prediv(volatile void *pllbase)
 123 {
 124 #ifdef CONFIG_SOC_DM355
 125         /* this register read seems to fail on pll0 */
 126         if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
 127                 return 8;
 128         else
 129                 return pll_div(pllbase, PLLC_PREDIV);
 130 #endif
 131         return 1;
 132 }
 133
 134 static inline unsigned pll_postdiv(volatile void *pllbase)
 135 {
 136 #ifdef CONFIG_SOC_DM355
 137         return pll_div(pllbase, PLLC_POSTDIV);
 138 #elif defined(CONFIG_SOC_DM6446)
 139         if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
 140                 return pll_div(pllbase, PLLC_POSTDIV);
 141 #endif
 142         return 1;
 143 }
 144
 145 static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 146 {
 147         volatile void   *pllbase = (volatile void *) pll_addr;
 148         unsigned        base = CONFIG_SYS_HZ_CLOCK / 1000;
 149
 150         /* the PLL might be bypassed */
 151         if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
 152                 base /= pll_prediv(pllbase);
 153                 base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
 154                 base /= pll_postdiv(pllbase);
 155         }
 156         return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
 157 }
 158
 159 int print_cpuinfo(void)
 160 {
 161         /* REVISIT fetch and display CPU ID and revision information
 162          * too ... that will matter as more revisions appear.
 163          */
 164         printf("Cores: ARM %d MHz",
 165                         pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
 166
 167 #ifdef DSP_PLLDIV
 168         printf(", DSP %d MHz",
 169                         pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
 170 #endif
 171
 172         printf("\nDDR:   %d MHz\n",
 173                         /* DDR PHY uses an x2 input clock */
 174                         pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
 175                                 / 2);
 176         return 0;
 177 }
 178
 179 #endif
 180
 181 /*
 182  * Initializes on-chip ethernet controllers.
 183  * to override, implement board_eth_init()
 184  */
 185 int cpu_eth_init(bd_t *bis)
 186 {
 187 #if defined(CONFIG_DRIVER_TI_EMAC)
 188         davinci_emac_initialize();
 189 #endif
 190         return 0;
 191 }