cpu/arm926ejs/davinci/nand.c

   1 /*
   2  * NAND driver for TI DaVinci based boards.
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  *
   6  * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
   7  */
   8
   9 /*
  10  *
  11  * linux/drivers/mtd/nand/nand_davinci.c
  12  *
  13  * NAND Flash Driver
  14  *
  15  * Copyright (C) 2006 Texas Instruments.
  16  *
  17  * ----------------------------------------------------------------------------
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  *  You should have received a copy of the GNU General Public License
  30  *  along with this program; if not, write to the Free Software
  31  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  32  * ----------------------------------------------------------------------------
  33  *
  34  *  Overview:
  35  *   This is a device driver for the NAND flash device found on the
  36  *   DaVinci board which utilizes the Samsung k9k2g08 part.
  37  *
  38  Modifications:
  39  ver. 1.0: Feb 2005, Vinod/Sudhakar
  40  -
  41  *
  42  */
  43
  44 #include <common.h>
  45
  46 #ifdef CFG_USE_NAND
  47 #if !defined(CFG_NAND_LEGACY)
  48
  49 #include <nand.h>
  50 #include <asm/arch/nand_defs.h>
  51 #include <asm/arch/emif_defs.h>
  52
  53 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
  54
  55 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd)
  56 {
  57         struct          nand_chip *this = mtd->priv;
  58         u_int32_t       IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
  59
  60         IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
  61
  62         switch (cmd) {
  63                 case NAND_CTL_SETCLE:
  64                         IO_ADDR_W |= MASK_CLE;
  65                         break;
  66                 case NAND_CTL_SETALE:
  67                         IO_ADDR_W |= MASK_ALE;
  68                         break;
  69         }
  70
  71         this->IO_ADDR_W = (void *)IO_ADDR_W;
  72 }
  73
  74 /* Set WP on deselect, write enable on select */
  75 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
  76 {
  77 #define GPIO_SET_DATA01 0x01c67018
  78 #define GPIO_CLR_DATA01 0x01c6701c
  79 #define GPIO_NAND_WP    (1 << 4)
  80 #ifdef SONATA_BOARD_GPIOWP
  81         if (chip < 0) {
  82                 REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
  83         } else {
  84                 REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
  85         }
  86 #endif
  87 }
  88
  89 #ifdef CFG_NAND_HW_ECC
  90 #ifdef CFG_NAND_LARGEPAGE
  91 static struct nand_oobinfo davinci_nand_oobinfo = {
  92         .useecc = MTD_NANDECC_AUTOPLACE,
  93         .eccbytes = 12,
  94         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
  95         .oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} }
  96 };
  97 #elif defined(CFG_NAND_SMALLPAGE)
  98 static struct nand_oobinfo davinci_nand_oobinfo = {
  99         .useecc = MTD_NANDECC_AUTOPLACE,
 100         .eccbytes = 3,
 101         .eccpos = {0, 1, 2},
 102         .oobfree = { {6, 2}, {8, 8} }
 103 };
 104 #else
 105 #error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
 106 #endif
 107
 108 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 109 {
 110         emifregs        emif_addr;
 111         int             dummy;
 112
 113         emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
 114
 115         dummy = emif_addr->NANDF1ECC;
 116         dummy = emif_addr->NANDF2ECC;
 117         dummy = emif_addr->NANDF3ECC;
 118         dummy = emif_addr->NANDF4ECC;
 119
 120         emif_addr->NANDFCR |= (1 << 8);
 121 }
 122
 123 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
 124 {
 125         u_int32_t       ecc = 0;
 126         emifregs        emif_base_addr;
 127
 128         emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
 129
 130         if (region == 1)
 131                 ecc = emif_base_addr->NANDF1ECC;
 132         else if (region == 2)
 133                 ecc = emif_base_addr->NANDF2ECC;
 134         else if (region == 3)
 135                 ecc = emif_base_addr->NANDF3ECC;
 136         else if (region == 4)
 137                 ecc = emif_base_addr->NANDF4ECC;
 138
 139         return(ecc);
 140 }
 141
 142 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 143 {
 144         u_int32_t               tmp;
 145         int                     region, n;
 146         struct nand_chip        *this = mtd->priv;
 147
 148         n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
 149
 150         region = 1;
 151         while (n--) {
 152                 tmp = nand_davinci_readecc(mtd, region);
 153                 *ecc_code++ = tmp;
 154                 *ecc_code++ = tmp >> 16;
 155                 *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
 156                 region++;
 157         }
 158         return(0);
 159 }
 160
 161 static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
 162 {
 163         u_int32_t       tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
 164
 165         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 166         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 167         ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 168 }
 169
 170 static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
 171 {
 172         u_int32_t       i;
 173         u_int8_t        tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 174         u_int8_t        comp0_bit[8], comp1_bit[8], comp2_bit[8];
 175         u_int8_t        ecc_bit[24];
 176         u_int8_t        ecc_sum = 0;
 177         u_int8_t        find_bit = 0;
 178         u_int32_t       find_byte = 0;
 179         int             is_ecc_ff;
 180
 181         is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
 182
 183         nand_davinci_gen_true_ecc(ecc_nand);
 184         nand_davinci_gen_true_ecc(ecc_calc);
 185
 186         for (i = 0; i <= 2; i++) {
 187                 *(ecc_nand + i) = ~(*(ecc_nand + i));
 188                 *(ecc_calc + i) = ~(*(ecc_calc + i));
 189         }
 190
 191         for (i = 0; i < 8; i++) {
 192                 tmp0_bit[i] = *ecc_nand % 2;
 193                 *ecc_nand = *ecc_nand / 2;
 194         }
 195
 196         for (i = 0; i < 8; i++) {
 197                 tmp1_bit[i] = *(ecc_nand + 1) % 2;
 198                 *(ecc_nand + 1) = *(ecc_nand + 1) / 2;
 199         }
 200
 201         for (i = 0; i < 8; i++) {
 202                 tmp2_bit[i] = *(ecc_nand + 2) % 2;
 203                 *(ecc_nand + 2) = *(ecc_nand + 2) / 2;
 204         }
 205
 206         for (i = 0; i < 8; i++) {
 207                 comp0_bit[i] = *ecc_calc % 2;
 208                 *ecc_calc = *ecc_calc / 2;
 209         }
 210
 211         for (i = 0; i < 8; i++) {
 212                 comp1_bit[i] = *(ecc_calc + 1) % 2;
 213                 *(ecc_calc + 1) = *(ecc_calc + 1) / 2;
 214         }
 215
 216         for (i = 0; i < 8; i++) {
 217                 comp2_bit[i] = *(ecc_calc + 2) % 2;
 218                 *(ecc_calc + 2) = *(ecc_calc + 2) / 2;
 219         }
 220
 221         for (i = 0; i< 6; i++)
 222                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 223
 224         for (i = 0; i < 8; i++)
 225                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 226
 227         for (i = 0; i < 8; i++)
 228                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 229
 230         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 231         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 232
 233         for (i = 0; i < 24; i++)
 234                 ecc_sum += ecc_bit[i];
 235
 236         switch (ecc_sum) {
 237                 case 0:
 238                         /* Not reached because this function is not called if
 239                            ECC values are equal */
 240                         return 0;
 241                 case 1:
 242                         /* Uncorrectable error */
 243                         DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 244                         return(-1);
 245                 case 12:
 246                         /* Correctable error */
 247                         find_byte = (ecc_bit[23] << 8) +
 248                                 (ecc_bit[21] << 7) +
 249                                 (ecc_bit[19] << 6) +
 250                                 (ecc_bit[17] << 5) +
 251                                 (ecc_bit[15] << 4) +
 252                                 (ecc_bit[13] << 3) +
 253                                 (ecc_bit[11] << 2) +
 254                                 (ecc_bit[9]  << 1) +
 255                                 ecc_bit[7];
 256
 257                         find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 258
 259                         DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit);
 260
 261                         page_data[find_byte] ^= (1 << find_bit);
 262
 263                         return(0);
 264                 default:
 265                         if (is_ecc_ff) {
 266                                 if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
 267                                         return(0);
 268                         }
 269                         DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
 270                         return(-1);
 271         }
 272 }
 273
 274 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
 275 {
 276         struct nand_chip        *this;
 277         int                     block_count = 0, i, rc;
 278
 279         this = mtd->priv;
 280         block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
 281         for (i = 0; i < block_count; i++) {
 282                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 283                         rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
 284                         if (rc < 0) {
 285                                 return(rc);
 286                         }
 287                 }
 288                 read_ecc += 3;
 289                 calc_ecc += 3;
 290                 dat += 512;
 291         }
 292         return(0);
 293 }
 294 #endif
 295
 296 static int nand_davinci_dev_ready(struct mtd_info *mtd)
 297 {
 298         emifregs        emif_addr;
 299
 300         emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
 301
 302         return(emif_addr->NANDFSR & 0x1);
 303 }
 304
 305 static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
 306 {
 307         while(!nand_davinci_dev_ready(mtd)) {;}
 308         *NAND_CE0CLE = NAND_STATUS;
 309         return(*NAND_CE0DATA);
 310 }
 311
 312 static void nand_flash_init(void)
 313 {
 314         u_int32_t       acfg1 = 0x3ffffffc;
 315         u_int32_t       acfg2 = 0x3ffffffc;
 316         u_int32_t       acfg3 = 0x3ffffffc;
 317         u_int32_t       acfg4 = 0x3ffffffc;
 318         emifregs        emif_regs;
 319
 320         /*------------------------------------------------------------------*
 321          *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
 322          *                                                                  *
 323          *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
 324          *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
 325          *                                                                  *
 326          *------------------------------------------------------------------*/
 327          acfg1 = 0
 328                 | (0 << 31 )    /* selectStrobe */
 329                 | (0 << 30 )    /* extWait */
 330                 | (1 << 26 )    /* writeSetup   10 ns */
 331                 | (3 << 20 )    /* writeStrobe  40 ns */
 332                 | (1 << 17 )    /* writeHold    10 ns */
 333                 | (1 << 13 )    /* readSetup    10 ns */
 334                 | (5 << 7 )     /* readStrobe   60 ns */
 335                 | (1 << 4 )     /* readHold     10 ns */
 336                 | (3 << 2 )     /* turnAround   ?? ns */
 337                 | (0 << 0 )     /* asyncSize    8-bit bus */
 338                 ;
 339
 340         emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
 341
 342         emif_regs->AWCCR |= 0x10000000;
 343         emif_regs->AB1CR = acfg1;       /* 0x08244128 */;
 344         emif_regs->AB2CR = acfg2;
 345         emif_regs->AB3CR = acfg3;
 346         emif_regs->AB4CR = acfg4;
 347         emif_regs->NANDFCR = 0x00000101;
 348 }
 349
 350 int board_nand_init(struct nand_chip *nand)
 351 {
 352         nand->IO_ADDR_R   = (void  __iomem *)NAND_CE0DATA;
 353         nand->IO_ADDR_W   = (void  __iomem *)NAND_CE0DATA;
 354         nand->chip_delay  = 0;
 355         nand->select_chip = nand_davinci_select_chip;
 356 #ifdef CFG_NAND_USE_FLASH_BBT
 357         nand->options     = NAND_USE_FLASH_BBT;
 358 #endif
 359 #ifdef CFG_NAND_HW_ECC
 360 #ifdef CFG_NAND_LARGEPAGE
 361         nand->eccmode     = NAND_ECC_HW12_2048;
 362 #elif defined(CFG_NAND_SMALLPAGE)
 363         nand->eccmode     = NAND_ECC_HW3_512;
 364 #else
 365 #error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
 366 #endif
 367         nand->autooob     = &davinci_nand_oobinfo;
 368         nand->calculate_ecc = nand_davinci_calculate_ecc;
 369         nand->correct_data  = nand_davinci_correct_data;
 370         nand->enable_hwecc  = nand_davinci_enable_hwecc;
 371 #else
 372         nand->eccmode     = NAND_ECC_SOFT;
 373 #endif
 374
 375         /* Set address of hardware control function */
 376         nand->hwcontrol = nand_davinci_hwcontrol;
 377
 378         nand->dev_ready = nand_davinci_dev_ready;
 379         nand->waitfunc = nand_davinci_waitfunc;
 380
 381         nand_flash_init();
 382
 383         return(0);
 384 }
 385
 386 #else
 387 #error "U-Boot legacy NAND support not available for DaVinci chips"
 388 #endif
 389 #endif  /* CFG_USE_NAND */