2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
35 * This is a device driver for the NAND flash device found on the
36 * DaVinci board which utilizes the Samsung k9k2g08 part.
39 ver. 1.0: Feb 2005, Vinod/Sudhakar
47 #if !defined(CFG_NAND_LEGACY)
50 #include <asm/arch/nand_defs.h>
51 #include <asm/arch/emif_defs.h>
53 extern struct nand_chip nand_dev_desc
[CFG_MAX_NAND_DEVICE
];
55 static void nand_davinci_hwcontrol(struct mtd_info
*mtd
, int cmd
)
57 struct nand_chip
*this = mtd
->priv
;
58 u_int32_t IO_ADDR_W
= (u_int32_t
)this->IO_ADDR_W
;
60 IO_ADDR_W
&= ~(MASK_ALE
|MASK_CLE
);
64 IO_ADDR_W
|= MASK_CLE
;
67 IO_ADDR_W
|= MASK_ALE
;
71 this->IO_ADDR_W
= (void *)IO_ADDR_W
;
74 /* Set WP on deselect, write enable on select */
75 static void nand_davinci_select_chip(struct mtd_info
*mtd
, int chip
)
77 #define GPIO_SET_DATA01 0x01c67018
78 #define GPIO_CLR_DATA01 0x01c6701c
79 #define GPIO_NAND_WP (1 << 4)
80 #ifdef SONATA_BOARD_GPIOWP
82 REG(GPIO_CLR_DATA01
) |= GPIO_NAND_WP
;
84 REG(GPIO_SET_DATA01
) |= GPIO_NAND_WP
;
89 #ifdef CFG_NAND_HW_ECC
90 #ifdef CFG_NAND_LARGEPAGE
91 static struct nand_oobinfo davinci_nand_oobinfo
= {
92 .useecc
= MTD_NANDECC_AUTOPLACE
,
94 .eccpos
= {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
95 .oobfree
= { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} }
97 #elif defined(CFG_NAND_SMALLPAGE)
98 static struct nand_oobinfo davinci_nand_oobinfo
= {
99 .useecc
= MTD_NANDECC_AUTOPLACE
,
102 .oobfree
= { {6, 2}, {8, 8} }
105 #error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
108 static void nand_davinci_enable_hwecc(struct mtd_info
*mtd
, int mode
)
113 emif_addr
= (emifregs
)DAVINCI_ASYNC_EMIF_CNTRL_BASE
;
115 dummy
= emif_addr
->NANDF1ECC
;
116 dummy
= emif_addr
->NANDF2ECC
;
117 dummy
= emif_addr
->NANDF3ECC
;
118 dummy
= emif_addr
->NANDF4ECC
;
120 emif_addr
->NANDFCR
|= (1 << 8);
123 static u_int32_t
nand_davinci_readecc(struct mtd_info
*mtd
, u_int32_t region
)
126 emifregs emif_base_addr
;
128 emif_base_addr
= (emifregs
)DAVINCI_ASYNC_EMIF_CNTRL_BASE
;
131 ecc
= emif_base_addr
->NANDF1ECC
;
132 else if (region
== 2)
133 ecc
= emif_base_addr
->NANDF2ECC
;
134 else if (region
== 3)
135 ecc
= emif_base_addr
->NANDF3ECC
;
136 else if (region
== 4)
137 ecc
= emif_base_addr
->NANDF4ECC
;
142 static int nand_davinci_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
, u_char
*ecc_code
)
146 struct nand_chip
*this = mtd
->priv
;
148 n
= (this->eccmode
== NAND_ECC_HW12_2048
) ? 4 : 1;
152 tmp
= nand_davinci_readecc(mtd
, region
);
154 *ecc_code
++ = tmp
>> 16;
155 *ecc_code
++ = ((tmp
>> 8) & 0x0f) | ((tmp
>> 20) & 0xf0);
161 static void nand_davinci_gen_true_ecc(u_int8_t
*ecc_buf
)
163 u_int32_t tmp
= ecc_buf
[0] | (ecc_buf
[1] << 16) | ((ecc_buf
[2] & 0xf0) << 20) | ((ecc_buf
[2] & 0x0f) << 8);
165 ecc_buf
[0] = ~(P64o(tmp
) | P64e(tmp
) | P32o(tmp
) | P32e(tmp
) | P16o(tmp
) | P16e(tmp
) | P8o(tmp
) | P8e(tmp
));
166 ecc_buf
[1] = ~(P1024o(tmp
) | P1024e(tmp
) | P512o(tmp
) | P512e(tmp
) | P256o(tmp
) | P256e(tmp
) | P128o(tmp
) | P128e(tmp
));
167 ecc_buf
[2] = ~( P4o(tmp
) | P4e(tmp
) | P2o(tmp
) | P2e(tmp
) | P1o(tmp
) | P1e(tmp
) | P2048o(tmp
) | P2048e(tmp
));
170 static int nand_davinci_compare_ecc(u_int8_t
*ecc_nand
, u_int8_t
*ecc_calc
, u_int8_t
*page_data
)
173 u_int8_t tmp0_bit
[8], tmp1_bit
[8], tmp2_bit
[8];
174 u_int8_t comp0_bit
[8], comp1_bit
[8], comp2_bit
[8];
175 u_int8_t ecc_bit
[24];
176 u_int8_t ecc_sum
= 0;
177 u_int8_t find_bit
= 0;
178 u_int32_t find_byte
= 0;
181 is_ecc_ff
= ((*ecc_nand
== 0xff) && (*(ecc_nand
+ 1) == 0xff) && (*(ecc_nand
+ 2) == 0xff));
183 nand_davinci_gen_true_ecc(ecc_nand
);
184 nand_davinci_gen_true_ecc(ecc_calc
);
186 for (i
= 0; i
<= 2; i
++) {
187 *(ecc_nand
+ i
) = ~(*(ecc_nand
+ i
));
188 *(ecc_calc
+ i
) = ~(*(ecc_calc
+ i
));
191 for (i
= 0; i
< 8; i
++) {
192 tmp0_bit
[i
] = *ecc_nand
% 2;
193 *ecc_nand
= *ecc_nand
/ 2;
196 for (i
= 0; i
< 8; i
++) {
197 tmp1_bit
[i
] = *(ecc_nand
+ 1) % 2;
198 *(ecc_nand
+ 1) = *(ecc_nand
+ 1) / 2;
201 for (i
= 0; i
< 8; i
++) {
202 tmp2_bit
[i
] = *(ecc_nand
+ 2) % 2;
203 *(ecc_nand
+ 2) = *(ecc_nand
+ 2) / 2;
206 for (i
= 0; i
< 8; i
++) {
207 comp0_bit
[i
] = *ecc_calc
% 2;
208 *ecc_calc
= *ecc_calc
/ 2;
211 for (i
= 0; i
< 8; i
++) {
212 comp1_bit
[i
] = *(ecc_calc
+ 1) % 2;
213 *(ecc_calc
+ 1) = *(ecc_calc
+ 1) / 2;
216 for (i
= 0; i
< 8; i
++) {
217 comp2_bit
[i
] = *(ecc_calc
+ 2) % 2;
218 *(ecc_calc
+ 2) = *(ecc_calc
+ 2) / 2;
221 for (i
= 0; i
< 6; i
++)
222 ecc_bit
[i
] = tmp2_bit
[i
+ 2] ^ comp2_bit
[i
+ 2];
224 for (i
= 0; i
< 8; i
++)
225 ecc_bit
[i
+ 6] = tmp0_bit
[i
] ^ comp0_bit
[i
];
227 for (i
= 0; i
< 8; i
++)
228 ecc_bit
[i
+ 14] = tmp1_bit
[i
] ^ comp1_bit
[i
];
230 ecc_bit
[22] = tmp2_bit
[0] ^ comp2_bit
[0];
231 ecc_bit
[23] = tmp2_bit
[1] ^ comp2_bit
[1];
233 for (i
= 0; i
< 24; i
++)
234 ecc_sum
+= ecc_bit
[i
];
238 /* Not reached because this function is not called if
239 ECC values are equal */
242 /* Uncorrectable error */
243 DEBUG (MTD_DEBUG_LEVEL0
, "ECC UNCORRECTED_ERROR 1\n");
246 /* Correctable error */
247 find_byte
= (ecc_bit
[23] << 8) +
257 find_bit
= (ecc_bit
[5] << 2) + (ecc_bit
[3] << 1) + ecc_bit
[1];
259 DEBUG (MTD_DEBUG_LEVEL0
, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte
, find_bit
);
261 page_data
[find_byte
] ^= (1 << find_bit
);
266 if (ecc_calc
[0] == 0 && ecc_calc
[1] == 0 && ecc_calc
[2] == 0)
269 DEBUG (MTD_DEBUG_LEVEL0
, "UNCORRECTED_ERROR default\n");
274 static int nand_davinci_correct_data(struct mtd_info
*mtd
, u_char
*dat
, u_char
*read_ecc
, u_char
*calc_ecc
)
276 struct nand_chip
*this;
277 int block_count
= 0, i
, rc
;
280 block_count
= (this->eccmode
== NAND_ECC_HW12_2048
) ? 4 : 1;
281 for (i
= 0; i
< block_count
; i
++) {
282 if (memcmp(read_ecc
, calc_ecc
, 3) != 0) {
283 rc
= nand_davinci_compare_ecc(read_ecc
, calc_ecc
, dat
);
296 static int nand_davinci_dev_ready(struct mtd_info
*mtd
)
300 emif_addr
= (emifregs
)DAVINCI_ASYNC_EMIF_CNTRL_BASE
;
302 return(emif_addr
->NANDFSR
& 0x1);
305 static int nand_davinci_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*this, int state
)
307 while(!nand_davinci_dev_ready(mtd
)) {;}
308 *NAND_CE0CLE
= NAND_STATUS
;
309 return(*NAND_CE0DATA
);
312 static void nand_flash_init(void)
314 u_int32_t acfg1
= 0x3ffffffc;
315 u_int32_t acfg2
= 0x3ffffffc;
316 u_int32_t acfg3
= 0x3ffffffc;
317 u_int32_t acfg4
= 0x3ffffffc;
320 /*------------------------------------------------------------------*
321 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
323 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
324 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
326 *------------------------------------------------------------------*/
328 | (0 << 31 ) /* selectStrobe */
329 | (0 << 30 ) /* extWait */
330 | (1 << 26 ) /* writeSetup 10 ns */
331 | (3 << 20 ) /* writeStrobe 40 ns */
332 | (1 << 17 ) /* writeHold 10 ns */
333 | (1 << 13 ) /* readSetup 10 ns */
334 | (5 << 7 ) /* readStrobe 60 ns */
335 | (1 << 4 ) /* readHold 10 ns */
336 | (3 << 2 ) /* turnAround ?? ns */
337 | (0 << 0 ) /* asyncSize 8-bit bus */
340 emif_regs
= (emifregs
)DAVINCI_ASYNC_EMIF_CNTRL_BASE
;
342 emif_regs
->AWCCR
|= 0x10000000;
343 emif_regs
->AB1CR
= acfg1
; /* 0x08244128 */;
344 emif_regs
->AB2CR
= acfg2
;
345 emif_regs
->AB3CR
= acfg3
;
346 emif_regs
->AB4CR
= acfg4
;
347 emif_regs
->NANDFCR
= 0x00000101;
350 int board_nand_init(struct nand_chip
*nand
)
352 nand
->IO_ADDR_R
= (void __iomem
*)NAND_CE0DATA
;
353 nand
->IO_ADDR_W
= (void __iomem
*)NAND_CE0DATA
;
354 nand
->chip_delay
= 0;
355 nand
->select_chip
= nand_davinci_select_chip
;
356 #ifdef CFG_NAND_USE_FLASH_BBT
357 nand
->options
= NAND_USE_FLASH_BBT
;
359 #ifdef CFG_NAND_HW_ECC
360 #ifdef CFG_NAND_LARGEPAGE
361 nand
->eccmode
= NAND_ECC_HW12_2048
;
362 #elif defined(CFG_NAND_SMALLPAGE)
363 nand
->eccmode
= NAND_ECC_HW3_512
;
365 #error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
367 nand
->autooob
= &davinci_nand_oobinfo
;
368 nand
->calculate_ecc
= nand_davinci_calculate_ecc
;
369 nand
->correct_data
= nand_davinci_correct_data
;
370 nand
->enable_hwecc
= nand_davinci_enable_hwecc
;
372 nand
->eccmode
= NAND_ECC_SOFT
;
375 /* Set address of hardware control function */
376 nand
->hwcontrol
= nand_davinci_hwcontrol
;
378 nand
->dev_ready
= nand_davinci_dev_ready
;
379 nand
->waitfunc
= nand_davinci_waitfunc
;
387 #error "U-Boot legacy NAND support not available for DaVinci chips"
389 #endif /* CFG_USE_NAND */