cpu/arm946es/start.S

   1 /*
   2  *  armboot - Startup Code for ARM926EJS CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <gj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33
  34 #include <config.h>
  35 #include <version.h>
  36
  37 /*
  38  *************************************************************************
  39  *
  40  * Jump vector table as in table 3.1 in [1]
  41  *
  42  *************************************************************************
  43  */
  44
  45
  46 .globl _start
  47 _start:
  48         b       reset
  49         ldr     pc, _undefined_instruction
  50         ldr     pc, _software_interrupt
  51         ldr     pc, _prefetch_abort
  52         ldr     pc, _data_abort
  53         ldr     pc, _not_used
  54         ldr     pc, _irq
  55         ldr     pc, _fiq
  56
  57 _undefined_instruction:
  58         .word undefined_instruction
  59 _software_interrupt:
  60         .word software_interrupt
  61 _prefetch_abort:
  62         .word prefetch_abort
  63 _data_abort:
  64         .word data_abort
  65 _not_used:
  66         .word not_used
  67 _irq:
  68         .word irq
  69 _fiq:
  70         .word fiq
  71
  72         .balignl 16,0xdeadbeef
  73
  74
  75 /*
  76  *************************************************************************
  77  *
  78  * Startup Code (reset vector)
  79  *
  80  * do important init only if we don't start from memory!
  81  * setup Memory and board specific bits prior to relocation.
  82  * relocate armboot to ram
  83  * setup stack
  84  *
  85  *************************************************************************
  86  */
  87
  88 _TEXT_BASE:
  89         .word   TEXT_BASE
  90
  91 .globl _armboot_start
  92 _armboot_start:
  93         .word _start
  94
  95 /*
  96  * These are defined in the board-specific linker script.
  97  */
  98 .globl _bss_start
  99 _bss_start:
 100         .word __bss_start
 101
 102 .globl _bss_end
 103 _bss_end:
 104         .word _end
 105
 106 #ifdef CONFIG_USE_IRQ
 107 /* IRQ stack memory (calculated at run-time) */
 108 .globl IRQ_STACK_START
 109 IRQ_STACK_START:
 110         .word   0x0badc0de
 111
 112 /* IRQ stack memory (calculated at run-time) */
 113 .globl FIQ_STACK_START
 114 FIQ_STACK_START:
 115         .word 0x0badc0de
 116 #endif
 117
 118
 119 /*
 120  * the actual reset code
 121  */
 122
 123 reset:
 124         /*
 125          * set the cpu to SVC32 mode
 126          */
 127         mrs     r0,cpsr
 128         bic     r0,r0,#0x1f
 129         orr     r0,r0,#0xd3
 130         msr     cpsr,r0
 131
 132         /*
 133          * we do sys-critical inits only at reboot,
 134          * not when booting from ram!
 135          */
 136 #ifdef CONFIG_INIT_CRITICAL
 137         bl      cpu_init_crit
 138 #endif
 139
 140 relocate:                               /* relocate U-Boot to RAM           */
 141         adr     r0, _start              /* r0 <- current position of code   */
 142         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 143         cmp     r0, r1                  /* don't reloc during debug         */
 144         beq     stack_setup
 145
 146         ldr     r2, _armboot_start
 147         ldr     r3, _bss_start
 148         sub     r2, r3, r2              /* r2 <- size of armboot            */
 149         add     r2, r0, r2              /* r2 <- source end address         */
 150
 151 copy_loop:
 152         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 153         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 154         cmp     r0, r2                  /* until source end addreee [r2]    */
 155         ble     copy_loop
 156
 157         /* Set up the stack                                                 */
 158 stack_setup:
 159         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 160         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 161         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 162 #ifdef CONFIG_USE_IRQ
 163         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 164 #endif
 165         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 166
 167 clear_bss:
 168         ldr     r0, _bss_start          /* find start of bss segment        */
 169         ldr     r1, _bss_end            /* stop here                        */
 170         mov     r2, #0x00000000         /* clear                            */
 171
 172 clbss_l:str     r2, [r0]                /* clear loop...                    */
 173         add     r0, r0, #4
 174         cmp     r0, r1
 175         bne     clbss_l
 176
 177         ldr     pc, _start_armboot
 178
 179 _start_armboot:
 180         .word start_armboot
 181
 182
 183 /*
 184  *************************************************************************
 185  *
 186  * CPU_init_critical registers
 187  *
 188  * setup important registers
 189  * setup memory timing
 190  *
 191  *************************************************************************
 192  */
 193
 194
 195 cpu_init_crit:
 196         /*
 197          * flush v4 I/D caches
 198          */
 199         mov     r0, #0
 200         mcr     p15, 0, r0, c7, c5, 0   /* flush v4 I-cache */
 201         mcr     p15, 0, r0, c7, c6, 0   /* flush v4 D-cache */
 202
 203         /*
 204          * disable MMU stuff and caches
 205          */
 206         mrc     p15, 0, r0, c1, c0, 0
 207         bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
 208         bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
 209         orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
 210         orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 211         mcr     p15, 0, r0, c1, c0, 0
 212
 213         /*
 214          * Go setup Memory and board specific bits prior to relocation.
 215          */
 216         mov     ip, lr          /* perserve link reg across call */
 217         bl      lowlevel_init   /* go setup memory */
 218         mov     lr, ip          /* restore link */
 219         mov     pc, lr          /* back to my caller */
 220 /*
 221  *************************************************************************
 222  *
 223  * Interrupt handling
 224  *
 225  *************************************************************************
 226  */
 227
 228 @
 229 @ IRQ stack frame.
 230 @
 231 #define S_FRAME_SIZE    72
 232
 233 #define S_OLD_R0        68
 234 #define S_PSR           64
 235 #define S_PC            60
 236 #define S_LR            56
 237 #define S_SP            52
 238
 239 #define S_IP            48
 240 #define S_FP            44
 241 #define S_R10           40
 242 #define S_R9            36
 243 #define S_R8            32
 244 #define S_R7            28
 245 #define S_R6            24
 246 #define S_R5            20
 247 #define S_R4            16
 248 #define S_R3            12
 249 #define S_R2            8
 250 #define S_R1            4
 251 #define S_R0            0
 252
 253 #define MODE_SVC 0x13
 254 #define I_BIT    0x80
 255
 256 /*
 257  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 258  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 259  */
 260
 261         .macro  bad_save_user_regs
 262         @ carve out a frame on current user stack
 263         sub     sp, sp, #S_FRAME_SIZE
 264         stmia   sp, {r0 - r12}  @ Save user registers (now in svc mode) r0-r12
 265
 266         ldr     r2, _armboot_start
 267         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 268         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 269         @ get values for "aborted" pc and cpsr (into parm regs)
 270         ldmia   r2, {r2 - r3}
 271         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 272         add     r5, sp, #S_SP
 273         mov     r1, lr
 274         stmia   r5, {r0 - r3}   @ save sp_SVC, lr_SVC, pc, cpsr
 275         mov     r0, sp          @ save current stack into r0 (param register)
 276         .endm
 277
 278         .macro  irq_save_user_regs
 279         sub     sp, sp, #S_FRAME_SIZE
 280         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 281         @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 282         add     r8, sp, #S_PC
 283         stmdb   r8, {sp, lr}^           @ Calling SP, LR
 284         str     lr, [r8, #0]            @ Save calling PC
 285         mrs     r6, spsr
 286         str     r6, [r8, #4]            @ Save CPSR
 287         str     r0, [r8, #8]            @ Save OLD_R0
 288         mov     r0, sp
 289         .endm
 290
 291         .macro  irq_restore_user_regs
 292         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 293         mov     r0, r0
 294         ldr     lr, [sp, #S_PC]                 @ Get PC
 295         add     sp, sp, #S_FRAME_SIZE
 296         subs    pc, lr, #4              @ return & move spsr_svc into cpsr
 297         .endm
 298
 299         .macro get_bad_stack
 300         ldr     r13, _armboot_start             @ setup our mode stack
 301         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 302         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 303
 304         str     lr, [r13]       @ save caller lr in position 0 of saved stack
 305         mrs     lr, spsr        @ get the spsr
 306         str     lr, [r13, #4]   @ save spsr in position 1 of saved stack
 307         mov     r13, #MODE_SVC  @ prepare SVC-Mode
 308         @ msr   spsr_c, r13
 309         msr     spsr, r13       @ switch modes, make sure moves will execute
 310         mov     lr, pc          @ capture return pc
 311         movs    pc, lr          @ jump to next instruction & switch modes.
 312         .endm
 313
 314         .macro get_irq_stack                    @ setup IRQ stack
 315         ldr     sp, IRQ_STACK_START
 316         .endm
 317
 318         .macro get_fiq_stack                    @ setup FIQ stack
 319         ldr     sp, FIQ_STACK_START
 320         .endm
 321
 322 /*
 323  * exception handlers
 324  */
 325         .align  5
 326 undefined_instruction:
 327         get_bad_stack
 328         bad_save_user_regs
 329         bl      do_undefined_instruction
 330
 331         .align  5
 332 software_interrupt:
 333         get_bad_stack
 334         bad_save_user_regs
 335         bl      do_software_interrupt
 336
 337         .align  5
 338 prefetch_abort:
 339         get_bad_stack
 340         bad_save_user_regs
 341         bl      do_prefetch_abort
 342
 343         .align  5
 344 data_abort:
 345         get_bad_stack
 346         bad_save_user_regs
 347         bl      do_data_abort
 348
 349         .align  5
 350 not_used:
 351         get_bad_stack
 352         bad_save_user_regs
 353         bl      do_not_used
 354
 355 #ifdef CONFIG_USE_IRQ
 356
 357         .align  5
 358 irq:
 359         get_irq_stack
 360         irq_save_user_regs
 361         bl      do_irq
 362         irq_restore_user_regs
 363
 364         .align  5
 365 fiq:
 366         get_fiq_stack
 367         /* someone ought to write a more effiction fiq_save_user_regs */
 368         irq_save_user_regs
 369         bl      do_fiq
 370         irq_restore_user_regs
 371
 372 #else
 373
 374         .align  5
 375 irq:
 376         get_bad_stack
 377         bad_save_user_regs
 378         bl      do_irq
 379
 380         .align  5
 381 fiq:
 382         get_bad_stack
 383         bad_save_user_regs
 384         bl      do_fiq
 385
 386 #endif
 387
 388 # ifdef CONFIG_INTEGRATOR
 389
 390         /* Satisfied by general board level routine */
 391
 392 #else
 393
 394         .align  5
 395 .globl reset_cpu
 396 reset_cpu:
 397
 398         ldr     r1, rstctl1     /* get clkm1 reset ctl */
 399         mov     r3, #0x0
 400         strh    r3, [r1]        /* clear it */
 401         mov     r3, #0x8
 402         strh    r3, [r1]        /* force dsp+arm reset */
 403 _loop_forever:
 404         b       _loop_forever
 405
 406 rstctl1:
 407         .word   0xfffece10
 408
 409 #endif  /* #ifdef CONFIG_INTEGRATOR */