cpu/arm_cortexa8/cpu.c

   1 /*
   2  * (C) Copyright 2008 Texas Insturments
   3  *
   4  * (C) Copyright 2002
   5  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * (C) Copyright 2002
   9  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * CPU specific code
  32  */
  33
  34 #include <common.h>
  35 #include <command.h>
  36 #include <asm/arch/sys_proto.h>
  37 #include <asm/system.h>
  38
  39 #ifdef CONFIG_USE_IRQ
  40 DECLARE_GLOBAL_DATA_PTR;
  41 #endif
  42
  43 #ifndef CONFIG_L2_OFF
  44 void l2cache_disable(void);
  45 #endif
  46
  47 static void cache_flush(void);
  48
  49 int cpu_init(void)
  50 {
  51         /*
  52          * setup up stacks if necessary
  53          */
  54 #ifdef CONFIG_USE_IRQ
  55         IRQ_STACK_START =
  56             _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
  57         FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  58 #endif
  59         return 0;
  60 }
  61
  62 int cleanup_before_linux(void)
  63 {
  64         unsigned int i;
  65
  66         /*
  67          * this function is called just before we call linux
  68          * it prepares the processor for linux
  69          *
  70          * we turn off caches etc ...
  71          */
  72         disable_interrupts();
  73
  74         /* turn off I/D-cache */
  75         icache_disable();
  76         dcache_disable();
  77
  78         /* invalidate I-cache */
  79         cache_flush();
  80
  81 #ifndef CONFIG_L2_OFF
  82         /* turn off L2 cache */
  83         l2cache_disable();
  84         /* invalidate L2 cache also */
  85         v7_flush_dcache_all(get_device_type());
  86 #endif
  87         i = 0;
  88         /* mem barrier to sync up things */
  89         asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
  90
  91 #ifndef CONFIG_L2_OFF
  92         l2cache_enable();
  93 #endif
  94
  95         return 0;
  96 }
  97
  98 void l2cache_enable()
  99 {
 100         unsigned long i;
 101         volatile unsigned int j;
 102
 103         /* ES2 onwards we can disable/enable L2 ourselves */
 104         if (get_cpu_rev() >= CPU_3XX_ES20) {
 105                 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 106                 __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
 107                 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
 108         } else {
 109                 /* Save r0, r12 and restore them after usage */
 110                 __asm__ __volatile__("mov %0, r12":"=r"(j));
 111                 __asm__ __volatile__("mov %0, r0":"=r"(i));
 112
 113                 /*
 114                  * GP Device ROM code API usage here
 115                  * r12 = AUXCR Write function and r0 value
 116                  */
 117                 __asm__ __volatile__("mov r12, #0x3");
 118                 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
 119                 __asm__ __volatile__("orr r0, r0, #0x2");
 120                 /* SMI instruction to call ROM Code API */
 121                 __asm__ __volatile__(".word 0xE1600070");
 122                 __asm__ __volatile__("mov r0, %0":"=r"(i));
 123                 __asm__ __volatile__("mov r12, %0":"=r"(j));
 124         }
 125
 126 }
 127
 128 void l2cache_disable()
 129 {
 130         unsigned long i;
 131         volatile unsigned int j;
 132
 133         /* ES2 onwards we can disable/enable L2 ourselves */
 134         if (get_cpu_rev() >= CPU_3XX_ES20) {
 135                 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 136                 __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
 137                 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
 138         } else {
 139                 /* Save r0, r12 and restore them after usage */
 140                 __asm__ __volatile__("mov %0, r12":"=r"(j));
 141                 __asm__ __volatile__("mov %0, r0":"=r"(i));
 142
 143                 /*
 144                  * GP Device ROM code API usage here
 145                  * r12 = AUXCR Write function and r0 value
 146                  */
 147                 __asm__ __volatile__("mov r12, #0x3");
 148                 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
 149                 __asm__ __volatile__("bic r0, r0, #0x2");
 150                 /* SMI instruction to call ROM Code API */
 151                 __asm__ __volatile__(".word 0xE1600070");
 152                 __asm__ __volatile__("mov r0, %0":"=r"(i));
 153                 __asm__ __volatile__("mov r12, %0":"=r"(j));
 154         }
 155 }
 156
 157 static void cache_flush(void)
 158 {
 159         asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 160 }