cpu/arm_cortexa8/omap3/sys_info.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *      Manikandan Pillai <mani.pillai@ti.com>
   7  *
   8  * Derived from Beagle Board and 3430 SDP code by
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <khasim@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/mem.h>       /* get mem tables */
  31 #include <asm/arch/sys_proto.h>
  32 #include <i2c.h>
  33
  34 extern omap3_sysinfo sysinfo;
  35 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
  36 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  37 static char *rev_s[CPU_3XX_MAX_REV] = {
  38                                 "1.0",
  39                                 "2.0",
  40                                 "2.1",
  41                                 "3.0",
  42                                 "3.1"};
  43
  44 /*****************************************************************
  45  * dieid_num_r(void) - read and set die ID
  46  *****************************************************************/
  47 void dieid_num_r(void)
  48 {
  49         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
  50         char *uid_s, die_id[34];
  51         u32 id[4];
  52
  53         memset(die_id, 0, sizeof(die_id));
  54
  55         uid_s = getenv("dieid#");
  56
  57         if (uid_s == NULL) {
  58                 id[3] = readl(&id_base->die_id_0);
  59                 id[2] = readl(&id_base->die_id_1);
  60                 id[1] = readl(&id_base->die_id_2);
  61                 id[0] = readl(&id_base->die_id_3);
  62                 sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
  63                 setenv("dieid#", die_id);
  64                 uid_s = die_id;
  65         }
  66
  67         printf("Die ID #%s\n", uid_s);
  68 }
  69
  70 /******************************************
  71  * get_cpu_type(void) - extract cpu info
  72  ******************************************/
  73 u32 get_cpu_type(void)
  74 {
  75         return readl(&ctrl_base->ctrl_omap_stat);
  76 }
  77
  78 /******************************************
  79  * get_cpu_rev(void) - extract version info
  80  ******************************************/
  81 u32 get_cpu_rev(void)
  82 {
  83         u32 cpuid = 0;
  84         struct ctrl_id *id_base;
  85
  86         /*
  87          * On ES1.0 the IDCODE register is not exposed on L4
  88          * so using CPU ID to differentiate between ES1.0 and > ES1.0.
  89          */
  90         __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
  91         if ((cpuid & 0xf) == 0x0)
  92                 return CPU_3XX_ES10;
  93         else {
  94                 /* Decode the IDs on > ES1.0 */
  95                 id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
  96
  97                 cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
  98
  99                 /* Some early ES2.0 seem to report ID 0, fix this */
 100                 if(cpuid == 0)
 101                         cpuid = CPU_3XX_ES20;
 102
 103                 return cpuid;
 104         }
 105 }
 106
 107 /****************************************************
 108  * is_mem_sdr() - return 1 if mem type in use is SDR
 109  ****************************************************/
 110 u32 is_mem_sdr(void)
 111 {
 112         if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
 113                 return 1;
 114         return 0;
 115 }
 116
 117 /***********************************************************************
 118  * get_cs0_size() - get size of chip select 0/1
 119  ************************************************************************/
 120 u32 get_sdr_cs_size(u32 cs)
 121 {
 122         u32 size;
 123
 124         /* get ram size field */
 125         size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
 126         size &= 0x3FF;          /* remove unwanted bits */
 127         size <<= 21;            /* multiply by 2 MiB to find size in MB */
 128         return size;
 129 }
 130
 131 /***********************************************************************
 132  * get_sdr_cs_offset() - get offset of cs from cs0 start
 133  ************************************************************************/
 134 u32 get_sdr_cs_offset(u32 cs)
 135 {
 136         u32 offset;
 137
 138         if (!cs)
 139                 return 0;
 140
 141         offset = readl(&sdrc_base->cs_cfg);
 142         offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
 143
 144         return offset;
 145 }
 146
 147 /***************************************************************************
 148  *  get_gpmc0_base() - Return current address hardware will be
 149  *     fetching from. The below effectively gives what is correct, its a bit
 150  *   mis-leading compared to the TRM.  For the most general case the mask
 151  *   needs to be also taken into account this does work in practice.
 152  *   - for u-boot we currently map:
 153  *       -- 0 to nothing,
 154  *       -- 4 to flash
 155  *       -- 8 to enent
 156  *       -- c to wifi
 157  ****************************************************************************/
 158 u32 get_gpmc0_base(void)
 159 {
 160         u32 b;
 161
 162         b = readl(&gpmc_cfg->cs[0].config7);
 163         b &= 0x1F;              /* keep base [5:0] */
 164         b = b << 24;            /* ret 0x0b000000 */
 165         return b;
 166 }
 167
 168 /*******************************************************************
 169  * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
 170  *******************************************************************/
 171 u32 get_gpmc0_width(void)
 172 {
 173         return WIDTH_16BIT;
 174 }
 175
 176 /*************************************************************************
 177  * get_board_rev() - setup to pass kernel board revision information
 178  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 179  *************************************************************************/
 180 u32 get_board_rev(void)
 181 {
 182         return 0x20;
 183 }
 184
 185 /********************************************************
 186  *  get_base(); get upper addr of current execution
 187  *******************************************************/
 188 u32 get_base(void)
 189 {
 190         u32 val;
 191
 192         __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
 193         val &= 0xF0000000;
 194         val >>= 28;
 195         return val;
 196 }
 197
 198 /********************************************************
 199  *  is_running_in_flash() - tell if currently running in
 200  *  FLASH.
 201  *******************************************************/
 202 u32 is_running_in_flash(void)
 203 {
 204         if (get_base() < 4)
 205                 return 1;       /* in FLASH */
 206
 207         return 0;               /* running in SRAM or SDRAM */
 208 }
 209
 210 /********************************************************
 211  *  is_running_in_sram() - tell if currently running in
 212  *  SRAM.
 213  *******************************************************/
 214 u32 is_running_in_sram(void)
 215 {
 216         if (get_base() == 4)
 217                 return 1;       /* in SRAM */
 218
 219         return 0;               /* running in FLASH or SDRAM */
 220 }
 221
 222 /********************************************************
 223  *  is_running_in_sdram() - tell if currently running in
 224  *  SDRAM.
 225  *******************************************************/
 226 u32 is_running_in_sdram(void)
 227 {
 228         if (get_base() > 4)
 229                 return 1;       /* in SDRAM */
 230
 231         return 0;               /* running in SRAM or FLASH */
 232 }
 233
 234 /***************************************************************
 235  *  get_boot_type() - Is this an XIP type device or a stream one
 236  *  bits 4-0 specify type. Bit 5 says mem/perif
 237  ***************************************************************/
 238 u32 get_boot_type(void)
 239 {
 240         return (readl(&ctrl_base->status) & SYSBOOT_MASK);
 241 }
 242
 243 /*************************************************************
 244  *  get_device_type(): tell if GP/HS/EMU/TST
 245  *************************************************************/
 246 u32 get_device_type(void)
 247 {
 248         return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 249 }
 250
 251 #ifdef CONFIG_DISPLAY_CPUINFO
 252 /**
 253  * Print CPU information
 254  */
 255 int print_cpuinfo (void)
 256 {
 257         char *cpu_s, *sec_s;
 258
 259         switch (get_cpu_type()) {
 260         case OMAP3503:
 261                 cpu_s = "3503";
 262                 break;
 263         case OMAP3515:
 264                 cpu_s = "3515";
 265                 break;
 266         case OMAP3525:
 267                 cpu_s = "3525";
 268                 break;
 269         case OMAP3530:
 270                 cpu_s = "3530";
 271                 break;
 272         default:
 273                 cpu_s = "35XX";
 274                 break;
 275         }
 276
 277         switch (get_device_type()) {
 278         case TST_DEVICE:
 279                 sec_s = "TST";
 280                 break;
 281         case EMU_DEVICE:
 282                 sec_s = "EMU";
 283                 break;
 284         case HS_DEVICE:
 285                 sec_s = "HS";
 286                 break;
 287         case GP_DEVICE:
 288                 sec_s = "GP";
 289                 break;
 290         default:
 291                 sec_s = "?";
 292         }
 293
 294         printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
 295                         cpu_s, sec_s, rev_s[get_cpu_rev()]);
 296
 297         return 0;
 298 }
 299 #endif  /* CONFIG_DISPLAY_CPUINFO */