cpu/at91rm9200/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8  * Alex Zuepke <azu@sysgo.de>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * CPU specific code
  31  */
  32
  33 #include <common.h>
  34 #include <command.h>
  35 #include <AT91RM9200.h>
  36
  37 /* read co-processor 15, register #1 (control register) */
  38 static unsigned long read_p15_c1(void)
  39 {
  40     unsigned long value;
  41
  42     __asm__ __volatile__(
  43         "mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
  44         : "=r" (value)
  45         :
  46         : "memory");
  47     /*printf("p15/c1 is = %08lx\n", value); */
  48     return value;
  49 }
  50
  51 /* write to co-processor 15, register #1 (control register) */
  52 static void write_p15_c1(unsigned long value)
  53 {
  54     /*printf("write %08lx to p15/c1\n", value); */
  55     __asm__ __volatile__(
  56         "mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
  57         : "=r" (value)
  58         :
  59         : "memory");
  60
  61     read_p15_c1();
  62 }
  63
  64 static void cp_delay(void)
  65 {
  66     volatile int i;
  67
  68     /* copro seems to need some delay between reading and writing */
  69     for (i=0; i<100; i++);
  70 }
  71 /* See also ARM Ref. Man. */
  72 #define C1_MMU          (1<<0)  /* mmu off/on */
  73 #define C1_ALIGN        (1<<1)  /* alignment faults off/on */
  74 #define C1_IDC          (1<<2)  /* icache and/or dcache off/on */
  75 #define C1_WRITE_BUFFER (1<<3)  /* write buffer off/on */
  76 #define C1_BIG_ENDIAN   (1<<7)  /* big endian off/on */
  77 #define C1_SYS_PROT     (1<<8)  /* system protection */
  78 #define C1_ROM_PROT     (1<<9)  /* ROM protection */
  79 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
  80
  81 int cpu_init(void)
  82 {
  83     /*
  84      * setup up stack if necessary
  85      */
  86 #ifdef CONFIG_USE_IRQ
  87     IRQ_STACK_START = _armboot_end +
  88                         CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
  89     FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
  90     _armboot_real_end = FIQ_STACK_START + 4;
  91 #else
  92     _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
  93 #endif
  94     return 0;
  95 }
  96
  97 int cleanup_before_linux(void)
  98 {
  99     /*
 100      * this function is called just before we call linux
 101      * it prepares the processor for linux
 102      *
 103      * we turn off caches etc ...
 104      * and we set the CPU-speed to 73 MHz - see start.S for details
 105      */
 106
 107     disable_interrupts();
 108     return 0;
 109 }
 110
 111 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 112 {
 113
 114 #ifdef CFG_SOFT_RESET
 115     extern void reset_cpu(ulong addr);
 116
 117     disable_interrupts();
 118     reset_cpu(0);
 119 #else
 120    AT91PS_USART us = AT91C_BASE_US1;
 121    AT91PS_PIO pio = AT91C_BASE_PIOA;
 122
 123    /*shutdown the console to avoid strange chars during reset */
 124    us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
 125
 126    /* Clear PA19 to trigger the hard reset */
 127    pio->PIO_CODR = 0x00080000;
 128    pio->PIO_OER  = 0x00080000;
 129    pio->PIO_PER  = 0x00080000;
 130    /* Never reached */
 131 #endif
 132    return 0;
 133 }
 134
 135 void icache_enable(void)
 136 {
 137     ulong reg;
 138     reg = read_p15_c1();
 139     cp_delay();
 140     write_p15_c1(reg | C1_IDC);
 141 }
 142
 143 void icache_disable(void)
 144 {
 145     ulong reg;
 146     reg = read_p15_c1();
 147     cp_delay();
 148     write_p15_c1(reg & ~C1_IDC);
 149 }
 150
 151 int icache_status(void)
 152 {
 153     return (read_p15_c1() & C1_IDC) != 0;
 154     return 0;
 155 }
 156
 157 void dcache_enable(void)
 158 {
 159     ulong reg;
 160     reg = read_p15_c1();
 161     cp_delay();
 162     write_p15_c1(reg | C1_IDC);
 163 }
 164
 165 void dcache_disable(void)
 166 {
 167     ulong reg;
 168     reg = read_p15_c1();
 169     cp_delay();
 170     write_p15_c1(reg & ~C1_IDC);
 171 }
 172
 173 int dcache_status(void)
 174 {
 175     return (read_p15_c1() & C1_IDC) != 0;
 176     return 0;
 177 }