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* Patch by Marc Singer, 29 May 2003:
[people/ms/u-boot.git] / cpu / i386 / interrupts.c
1 /*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <syscall.h>
26 #include <malloc.h>
27 #include <asm/io.h>
28 #include <asm/i8259.h>
29 #include <asm/ibmpc.h>
30
31
32
33 struct idt_entry {
34 u16 base_low;
35 u16 selector;
36 u8 res;
37 u8 access;
38 u16 base_high;
39 } __attribute__ ((packed));
40
41
42 struct idt_entry idt[256];
43
44
45 #define MAX_IRQ 16
46
47 typedef struct irq_handler {
48 struct irq_handler *next;
49 interrupt_handler_t* isr_func;
50 void *isr_data;
51 } irq_handler_t;
52
53 #define IRQ_DISABLED 1
54
55 typedef struct {
56 irq_handler_t *handler;
57 unsigned long status;
58 } irq_desc_t;
59
60 static irq_desc_t irq_table[MAX_IRQ];
61
62
63
64 asm(".globl syscall_entry\n" \
65 "syscall_entry:\n" \
66 "popl %ebx\n" /* throw away the return address, flags */ \
67 "popl %ebx\n" /* and segment that the INT instruction pushed */ \
68 "popl %ebx\n" /* on to the stack */ \
69 "movl %eax, %ecx\n" /* load the syscall nr argument*/ \
70 "movl syscall_tbl, %eax\n" /* load start of syscall table */ \
71 "cmpl $(11-1), %ecx\n" /* FixMe: find a way to use NR_SYSCALLS macro here */ \
72 "ja bad_syscall\n" \
73 "movl (%eax, %ecx, 4), %eax\n" /* load the handler of the syscall*/ \
74 "test %eax, %eax\n" /* test for null */ \
75 "je bad_syscall\n" \
76 "popl %ecx\n" \
77 "popl %ebx\n" \
78 "sti \n" \
79 "jmp *%eax\n" \
80 "bad_syscall: movl $0xffffffff, %eax\n" \
81 "popl %ecx\n" \
82 "popl %ebx\n" \
83 "ret");
84
85 void __attribute__ ((regparm(0))) syscall_entry(void);
86
87
88 asm ("irq_return:\n"
89 " addl $4, %esp\n"
90 " popa\n"
91 " iret\n");
92
93 asm ("exp_return:\n"
94 " addl $12, %esp\n"
95 " pop %esp\n"
96 " popa\n"
97 " iret\n");
98
99 char exception_stack[4096];
100
101 #define DECLARE_INTERRUPT(x) \
102 asm(".globl irq_"#x"\n" \
103 "irq_"#x":\n" \
104 "pusha \n" \
105 "pushl $"#x"\n" \
106 "pushl $irq_return\n" \
107 "jmp do_irq\n"); \
108 void __attribute__ ((regparm(0))) irq_##x(void)
109
110 #define DECLARE_EXCEPTION(x, f) \
111 asm(".globl exp_"#x"\n" \
112 "exp_"#x":\n" \
113 "pusha \n" \
114 "movl %esp, %ebx\n" \
115 "movl $exception_stack, %eax\n" \
116 "movl %eax, %esp \n" \
117 "pushl %ebx\n" \
118 "movl 32(%esp), %ebx\n" \
119 "xorl %edx, %edx\n" \
120 "movw 36(%esp), %dx\n" \
121 "pushl %edx\n" \
122 "pushl %ebx\n" \
123 "pushl $"#x"\n" \
124 "pushl $exp_return\n" \
125 "jmp "#f"\n"); \
126 void __attribute__ ((regparm(0))) exp_##x(void)
127
128 DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */
129 DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */
130 DECLARE_EXCEPTION(2, nmi_entry); /* NMI */
131 DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */
132 DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */
133 DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */
134 DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */
135 DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */
136 DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */
137 DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */
138 DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */
139 DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */
140 DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */
141 DECLARE_EXCEPTION(13, gpf_entry); /* GPF */
142 DECLARE_EXCEPTION(14, page_fault_entry); /* PF */
143 DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */
144 DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */
145 DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */
146 DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */
147 DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */
148 DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */
149 DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */
150 DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */
151 DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */
152 DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */
153 DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */
154 DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */
155 DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */
156 DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */
157 DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */
158 DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */
159 DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */
160
161 DECLARE_INTERRUPT(0);
162 DECLARE_INTERRUPT(1);
163 DECLARE_INTERRUPT(3);
164 DECLARE_INTERRUPT(4);
165 DECLARE_INTERRUPT(5);
166 DECLARE_INTERRUPT(6);
167 DECLARE_INTERRUPT(7);
168 DECLARE_INTERRUPT(8);
169 DECLARE_INTERRUPT(9);
170 DECLARE_INTERRUPT(10);
171 DECLARE_INTERRUPT(11);
172 DECLARE_INTERRUPT(12);
173 DECLARE_INTERRUPT(13);
174 DECLARE_INTERRUPT(14);
175 DECLARE_INTERRUPT(15);
176
177 void __attribute__ ((regparm(0))) default_isr(void);
178 asm ("default_isr: iret\n");
179
180 void disable_irq(int irq)
181 {
182 if (irq >= MAX_IRQ) {
183 return;
184 }
185 irq_table[irq].status |= IRQ_DISABLED;
186
187 }
188
189 void enable_irq(int irq)
190 {
191 if (irq >= MAX_IRQ) {
192 return;
193 }
194 irq_table[irq].status &= ~IRQ_DISABLED;
195 }
196
197 /* masks one specific IRQ in the PIC */
198 static void unmask_irq(int irq)
199 {
200 int imr_port;
201
202 if (irq >= MAX_IRQ) {
203 return;
204 }
205 if (irq > 7) {
206 imr_port = SLAVE_PIC + IMR;
207 } else {
208 imr_port = MASTER_PIC + IMR;
209 }
210
211 outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
212 }
213
214
215 /* unmasks one specific IRQ in the PIC */
216 static void mask_irq(int irq)
217 {
218 int imr_port;
219
220 if (irq >= MAX_IRQ) {
221 return;
222 }
223 if (irq > 7) {
224 imr_port = SLAVE_PIC + IMR;
225 } else {
226 imr_port = MASTER_PIC + IMR;
227 }
228
229 outb(inb(imr_port)|(1<<(irq&7)), imr_port);
230 }
231
232
233 /* issue a Specific End Of Interrupt instruciton */
234 static void specific_eoi(int irq)
235 {
236 /* If it is on the slave PIC this have to be performed on
237 * both the master and the slave PICs */
238 if (irq > 7) {
239 outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
240 irq = SEOI_IR2; /* also do IR2 on master */
241 }
242 outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
243 }
244
245 void __attribute__ ((regparm(0))) do_irq(int irq)
246 {
247
248 mask_irq(irq);
249
250 if (irq_table[irq].status & IRQ_DISABLED) {
251 unmask_irq(irq);
252 specific_eoi(irq);
253 return;
254 }
255
256
257 if (NULL != irq_table[irq].handler) {
258 irq_handler_t *handler;
259 for (handler = irq_table[irq].handler;
260 NULL!= handler; handler = handler->next) {
261 handler->isr_func(handler->isr_data);
262 }
263 } else {
264 if ((irq & 7) != 7) {
265 printf("Spurious irq %d\n", irq);
266 }
267 }
268 unmask_irq(irq);
269 specific_eoi(irq);
270 }
271
272
273 void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
274 {
275 printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
276 }
277
278 void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
279 {
280 printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
281 while(1);
282 }
283
284 void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
285 {
286 printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
287 }
288
289 void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
290 {
291 printf("NMI Interrupt at %04x:%08x\n", seg, ip);
292 }
293
294 void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
295 {
296 printf("Invalid Instruction at %04x:%08x\n", seg, ip);
297 while(1);
298 }
299
300 void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
301 {
302 printf("Double fault at %04x:%08x\n", seg, ip);
303 while(1);
304 }
305
306 void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
307 {
308 printf("Invalid TSS at %04x:%08x\n", seg, ip);
309 }
310
311 void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
312 {
313 printf("Segmentation fault at %04x:%08x\n", seg, ip);
314 while(1);
315 }
316
317 void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
318 {
319 printf("Stack fault at %04x:%08x\n", seg, ip);
320 while(1);
321 }
322
323 void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
324 {
325 printf("General protection fault at %04x:%08x\n", seg, ip);
326 }
327
328 void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
329 {
330 printf("Page fault at %04x:%08x\n", seg, ip);
331 while(1);
332 }
333
334 void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
335 {
336 printf("Floating point exception at %04x:%08x\n", seg, ip);
337 }
338
339 void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
340 {
341 printf("Alignment check at %04x:%08x\n", seg, ip);
342 }
343
344 void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
345 {
346 printf("Machine check exception at %04x:%08x\n", seg, ip);
347 }
348
349
350 void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
351 {
352 int status;
353
354 if (ino>MAX_IRQ) {
355 return;
356 }
357
358 if (NULL != irq_table[ino].handler) {
359 return;
360 }
361
362 status = disable_interrupts();
363 irq_table[ino].handler = malloc(sizeof(irq_handler_t));
364 if (NULL == irq_table[ino].handler) {
365 return;
366 }
367
368 memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
369
370 irq_table[ino].handler->isr_func = func;
371 irq_table[ino].handler->isr_data = pdata;
372 if (status) {
373 enable_interrupts();
374 }
375
376 unmask_irq(ino);
377
378 return;
379 }
380
381 void irq_free_handler(int ino)
382 {
383 int status;
384 if (ino>MAX_IRQ) {
385 return;
386 }
387
388 status = disable_interrupts();
389 mask_irq(ino);
390 if (NULL == irq_table[ino].handler) {
391 return;
392 }
393 free(irq_table[ino].handler);
394 irq_table[ino].handler=NULL;
395 if (status) {
396 enable_interrupts();
397 }
398 return;
399 }
400
401
402 asm ("idt_ptr:\n"
403 ".word 0x800\n" /* size of the table 8*256 bytes */
404 ".long idt\n" /* offset */
405 ".word 0x18\n");/* data segment */
406
407 static void set_vector(int intnum, void *routine)
408 {
409 idt[intnum].base_high = (u16)((u32)(routine)>>16);
410 idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
411 }
412
413
414 int interrupt_init(void)
415 {
416 int i;
417
418 /* Just in case... */
419 disable_interrupts();
420
421 /* Initialize the IDT and stuff */
422
423
424 memset(irq_table, 0, sizeof(irq_table));
425
426 /* Setup the IDT */
427 for (i=0;i<256;i++) {
428 idt[i].access = 0x8e;
429 idt[i].res = 0;
430 idt[i].selector = 0x10;
431 set_vector(i, default_isr);
432 }
433
434 asm ("cs lidt idt_ptr\n");
435
436 /* Setup exceptions */
437 set_vector(0x00, exp_0);
438 set_vector(0x01, exp_1);
439 set_vector(0x02, exp_2);
440 set_vector(0x03, exp_3);
441 set_vector(0x04, exp_4);
442 set_vector(0x05, exp_5);
443 set_vector(0x06, exp_6);
444 set_vector(0x07, exp_7);
445 set_vector(0x08, exp_8);
446 set_vector(0x09, exp_9);
447 set_vector(0x0a, exp_10);
448 set_vector(0x0b, exp_11);
449 set_vector(0x0c, exp_12);
450 set_vector(0x0d, exp_13);
451 set_vector(0x0e, exp_14);
452 set_vector(0x0f, exp_15);
453 set_vector(0x10, exp_16);
454 set_vector(0x11, exp_17);
455 set_vector(0x12, exp_18);
456 set_vector(0x13, exp_19);
457 set_vector(0x14, exp_20);
458 set_vector(0x15, exp_21);
459 set_vector(0x16, exp_22);
460 set_vector(0x17, exp_23);
461 set_vector(0x18, exp_24);
462 set_vector(0x19, exp_25);
463 set_vector(0x1a, exp_26);
464 set_vector(0x1b, exp_27);
465 set_vector(0x1c, exp_28);
466 set_vector(0x1d, exp_29);
467 set_vector(0x1e, exp_30);
468 set_vector(0x1f, exp_31);
469
470
471 /* Setup interrupts */
472 set_vector(0x20, irq_0);
473 set_vector(0x21, irq_1);
474 set_vector(0x23, irq_3);
475 set_vector(0x24, irq_4);
476 set_vector(0x25, irq_5);
477 set_vector(0x26, irq_6);
478 set_vector(0x27, irq_7);
479 set_vector(0x28, irq_8);
480 set_vector(0x29, irq_9);
481 set_vector(0x2a, irq_10);
482 set_vector(0x2b, irq_11);
483 set_vector(0x2c, irq_12);
484 set_vector(0x2d, irq_13);
485 set_vector(0x2e, irq_14);
486 set_vector(0x2f, irq_15);
487 /* vectors 0x30-0x3f are reserved for irq 16-31 */
488 set_vector(0x40, syscall_entry);
489
490
491 /* Mask all interrupts */
492 outb(0xff, MASTER_PIC + IMR);
493 outb(0xff, SLAVE_PIC + IMR);
494
495 /* Master PIC */
496 outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
497 outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */
498 outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
499 outb(ICW4_PM, MASTER_PIC + ICW4);
500
501 for (i=0;i<8;i++) {
502 outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
503 }
504
505 /* Slave PIC */
506 outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
507 outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */
508 outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */
509 outb(ICW4_PM, SLAVE_PIC + ICW4);
510
511 for (i=0;i<8;i++) {
512 outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
513 }
514
515
516 /* enable cascade interrerupt */
517 outb(0xfb, MASTER_PIC + IMR);
518 outb(0xff, SLAVE_PIC + IMR);
519
520 /* It is now safe to enable interrupts */
521 enable_interrupts();
522
523 return 0;
524 }
525
526 void enable_interrupts(void)
527 {
528 asm("sti\n");
529 }
530
531 int disable_interrupts(void)
532 {
533 long flags;
534
535 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
536
537 return (flags&0x200); /* IE flags is bit 9 */
538 }
539
540
541 #ifdef CFG_RESET_GENERIC
542
543 void __attribute__ ((regparm(0))) generate_gpf(void);
544 asm(".globl generate_gpf\n"
545 "generate_gpf:\n"
546 "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
547 * exist */
548 void reset_cpu(ulong addr)
549 {
550 set_vector(13, generate_gpf); /* general protection fault handler */
551 set_vector(8, generate_gpf); /* double fault handler */
552 generate_gpf(); /* start the show */
553 }
554 #endif
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