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* Code cleanup:
[people/ms/u-boot.git] / cpu / i386 / interrupts.c
1 /*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <syscall.h>
26 #include <malloc.h>
27 #include <asm/io.h>
28 #include <asm/i8259.h>
29 #include <asm/ibmpc.h>
30
31
32 struct idt_entry {
33 u16 base_low;
34 u16 selector;
35 u8 res;
36 u8 access;
37 u16 base_high;
38 } __attribute__ ((packed));
39
40
41 struct idt_entry idt[256];
42
43
44 #define MAX_IRQ 16
45
46 typedef struct irq_handler {
47 struct irq_handler *next;
48 interrupt_handler_t* isr_func;
49 void *isr_data;
50 } irq_handler_t;
51
52 #define IRQ_DISABLED 1
53
54 typedef struct {
55 irq_handler_t *handler;
56 unsigned long status;
57 } irq_desc_t;
58
59 static irq_desc_t irq_table[MAX_IRQ];
60
61
62 asm(".globl syscall_entry\n" \
63 "syscall_entry:\n" \
64 "popl %ebx\n" /* throw away the return address, flags */ \
65 "popl %ebx\n" /* and segment that the INT instruction pushed */ \
66 "popl %ebx\n" /* on to the stack */ \
67 "movl %eax, %ecx\n" /* load the syscall nr argument*/ \
68 "movl syscall_tbl, %eax\n" /* load start of syscall table */ \
69 "cmpl $(11-1), %ecx\n" /* FixMe: find a way to use NR_SYSCALLS macro here */ \
70 "ja bad_syscall\n" \
71 "movl (%eax, %ecx, 4), %eax\n" /* load the handler of the syscall*/ \
72 "test %eax, %eax\n" /* test for null */ \
73 "je bad_syscall\n" \
74 "popl %ecx\n" \
75 "popl %ebx\n" \
76 "sti \n" \
77 "jmp *%eax\n" \
78 "bad_syscall: movl $0xffffffff, %eax\n" \
79 "popl %ecx\n" \
80 "popl %ebx\n" \
81 "ret");
82
83 void __attribute__ ((regparm(0))) syscall_entry(void);
84
85
86 asm ("irq_return:\n"
87 " addl $4, %esp\n"
88 " popa\n"
89 " iret\n");
90
91 asm ("exp_return:\n"
92 " addl $12, %esp\n"
93 " pop %esp\n"
94 " popa\n"
95 " iret\n");
96
97 char exception_stack[4096];
98
99 #define DECLARE_INTERRUPT(x) \
100 asm(".globl irq_"#x"\n" \
101 "irq_"#x":\n" \
102 "pusha \n" \
103 "pushl $"#x"\n" \
104 "pushl $irq_return\n" \
105 "jmp do_irq\n"); \
106 void __attribute__ ((regparm(0))) irq_##x(void)
107
108 #define DECLARE_EXCEPTION(x, f) \
109 asm(".globl exp_"#x"\n" \
110 "exp_"#x":\n" \
111 "pusha \n" \
112 "movl %esp, %ebx\n" \
113 "movl $exception_stack, %eax\n" \
114 "movl %eax, %esp \n" \
115 "pushl %ebx\n" \
116 "movl 32(%esp), %ebx\n" \
117 "xorl %edx, %edx\n" \
118 "movw 36(%esp), %dx\n" \
119 "pushl %edx\n" \
120 "pushl %ebx\n" \
121 "pushl $"#x"\n" \
122 "pushl $exp_return\n" \
123 "jmp "#f"\n"); \
124 void __attribute__ ((regparm(0))) exp_##x(void)
125
126 DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */
127 DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */
128 DECLARE_EXCEPTION(2, nmi_entry); /* NMI */
129 DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */
130 DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */
131 DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */
132 DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */
133 DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */
134 DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */
135 DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */
136 DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */
137 DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */
138 DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */
139 DECLARE_EXCEPTION(13, gpf_entry); /* GPF */
140 DECLARE_EXCEPTION(14, page_fault_entry); /* PF */
141 DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */
142 DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */
143 DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */
144 DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */
145 DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */
146 DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */
147 DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */
148 DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */
149 DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */
150 DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */
151 DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */
152 DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */
153 DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */
154 DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */
155 DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */
156 DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */
157 DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */
158
159 DECLARE_INTERRUPT(0);
160 DECLARE_INTERRUPT(1);
161 DECLARE_INTERRUPT(3);
162 DECLARE_INTERRUPT(4);
163 DECLARE_INTERRUPT(5);
164 DECLARE_INTERRUPT(6);
165 DECLARE_INTERRUPT(7);
166 DECLARE_INTERRUPT(8);
167 DECLARE_INTERRUPT(9);
168 DECLARE_INTERRUPT(10);
169 DECLARE_INTERRUPT(11);
170 DECLARE_INTERRUPT(12);
171 DECLARE_INTERRUPT(13);
172 DECLARE_INTERRUPT(14);
173 DECLARE_INTERRUPT(15);
174
175 void __attribute__ ((regparm(0))) default_isr(void);
176 asm ("default_isr: iret\n");
177
178 void disable_irq(int irq)
179 {
180 if (irq >= MAX_IRQ) {
181 return;
182 }
183 irq_table[irq].status |= IRQ_DISABLED;
184
185 }
186
187 void enable_irq(int irq)
188 {
189 if (irq >= MAX_IRQ) {
190 return;
191 }
192 irq_table[irq].status &= ~IRQ_DISABLED;
193 }
194
195 /* masks one specific IRQ in the PIC */
196 static void unmask_irq(int irq)
197 {
198 int imr_port;
199
200 if (irq >= MAX_IRQ) {
201 return;
202 }
203 if (irq > 7) {
204 imr_port = SLAVE_PIC + IMR;
205 } else {
206 imr_port = MASTER_PIC + IMR;
207 }
208
209 outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
210 }
211
212
213 /* unmasks one specific IRQ in the PIC */
214 static void mask_irq(int irq)
215 {
216 int imr_port;
217
218 if (irq >= MAX_IRQ) {
219 return;
220 }
221 if (irq > 7) {
222 imr_port = SLAVE_PIC + IMR;
223 } else {
224 imr_port = MASTER_PIC + IMR;
225 }
226
227 outb(inb(imr_port)|(1<<(irq&7)), imr_port);
228 }
229
230
231 /* issue a Specific End Of Interrupt instruciton */
232 static void specific_eoi(int irq)
233 {
234 /* If it is on the slave PIC this have to be performed on
235 * both the master and the slave PICs */
236 if (irq > 7) {
237 outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
238 irq = SEOI_IR2; /* also do IR2 on master */
239 }
240 outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
241 }
242
243 void __attribute__ ((regparm(0))) do_irq(int irq)
244 {
245
246 mask_irq(irq);
247
248 if (irq_table[irq].status & IRQ_DISABLED) {
249 unmask_irq(irq);
250 specific_eoi(irq);
251 return;
252 }
253
254
255 if (NULL != irq_table[irq].handler) {
256 irq_handler_t *handler;
257 for (handler = irq_table[irq].handler;
258 NULL!= handler; handler = handler->next) {
259 handler->isr_func(handler->isr_data);
260 }
261 } else {
262 if ((irq & 7) != 7) {
263 printf("Spurious irq %d\n", irq);
264 }
265 }
266 unmask_irq(irq);
267 specific_eoi(irq);
268 }
269
270
271 void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
272 {
273 printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
274 }
275
276 void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
277 {
278 printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
279 while(1);
280 }
281
282 void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
283 {
284 printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
285 }
286
287 void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
288 {
289 printf("NMI Interrupt at %04x:%08x\n", seg, ip);
290 }
291
292 void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
293 {
294 printf("Invalid Instruction at %04x:%08x\n", seg, ip);
295 while(1);
296 }
297
298 void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
299 {
300 printf("Double fault at %04x:%08x\n", seg, ip);
301 while(1);
302 }
303
304 void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
305 {
306 printf("Invalid TSS at %04x:%08x\n", seg, ip);
307 }
308
309 void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
310 {
311 printf("Segmentation fault at %04x:%08x\n", seg, ip);
312 while(1);
313 }
314
315 void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
316 {
317 printf("Stack fault at %04x:%08x\n", seg, ip);
318 while(1);
319 }
320
321 void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
322 {
323 printf("General protection fault at %04x:%08x\n", seg, ip);
324 }
325
326 void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
327 {
328 printf("Page fault at %04x:%08x\n", seg, ip);
329 while(1);
330 }
331
332 void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
333 {
334 printf("Floating point exception at %04x:%08x\n", seg, ip);
335 }
336
337 void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
338 {
339 printf("Alignment check at %04x:%08x\n", seg, ip);
340 }
341
342 void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
343 {
344 printf("Machine check exception at %04x:%08x\n", seg, ip);
345 }
346
347
348 void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
349 {
350 int status;
351
352 if (ino>MAX_IRQ) {
353 return;
354 }
355
356 if (NULL != irq_table[ino].handler) {
357 return;
358 }
359
360 status = disable_interrupts();
361 irq_table[ino].handler = malloc(sizeof(irq_handler_t));
362 if (NULL == irq_table[ino].handler) {
363 return;
364 }
365
366 memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
367
368 irq_table[ino].handler->isr_func = func;
369 irq_table[ino].handler->isr_data = pdata;
370 if (status) {
371 enable_interrupts();
372 }
373
374 unmask_irq(ino);
375
376 return;
377 }
378
379 void irq_free_handler(int ino)
380 {
381 int status;
382 if (ino>MAX_IRQ) {
383 return;
384 }
385
386 status = disable_interrupts();
387 mask_irq(ino);
388 if (NULL == irq_table[ino].handler) {
389 return;
390 }
391 free(irq_table[ino].handler);
392 irq_table[ino].handler=NULL;
393 if (status) {
394 enable_interrupts();
395 }
396 return;
397 }
398
399
400 asm ("idt_ptr:\n"
401 ".word 0x800\n" /* size of the table 8*256 bytes */
402 ".long idt\n" /* offset */
403 ".word 0x18\n");/* data segment */
404
405 static void set_vector(int intnum, void *routine)
406 {
407 idt[intnum].base_high = (u16)((u32)(routine)>>16);
408 idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
409 }
410
411
412 int interrupt_init(void)
413 {
414 int i;
415
416 /* Just in case... */
417 disable_interrupts();
418
419 /* Initialize the IDT and stuff */
420
421
422 memset(irq_table, 0, sizeof(irq_table));
423
424 /* Setup the IDT */
425 for (i=0;i<256;i++) {
426 idt[i].access = 0x8e;
427 idt[i].res = 0;
428 idt[i].selector = 0x10;
429 set_vector(i, default_isr);
430 }
431
432 asm ("cs lidt idt_ptr\n");
433
434 /* Setup exceptions */
435 set_vector(0x00, exp_0);
436 set_vector(0x01, exp_1);
437 set_vector(0x02, exp_2);
438 set_vector(0x03, exp_3);
439 set_vector(0x04, exp_4);
440 set_vector(0x05, exp_5);
441 set_vector(0x06, exp_6);
442 set_vector(0x07, exp_7);
443 set_vector(0x08, exp_8);
444 set_vector(0x09, exp_9);
445 set_vector(0x0a, exp_10);
446 set_vector(0x0b, exp_11);
447 set_vector(0x0c, exp_12);
448 set_vector(0x0d, exp_13);
449 set_vector(0x0e, exp_14);
450 set_vector(0x0f, exp_15);
451 set_vector(0x10, exp_16);
452 set_vector(0x11, exp_17);
453 set_vector(0x12, exp_18);
454 set_vector(0x13, exp_19);
455 set_vector(0x14, exp_20);
456 set_vector(0x15, exp_21);
457 set_vector(0x16, exp_22);
458 set_vector(0x17, exp_23);
459 set_vector(0x18, exp_24);
460 set_vector(0x19, exp_25);
461 set_vector(0x1a, exp_26);
462 set_vector(0x1b, exp_27);
463 set_vector(0x1c, exp_28);
464 set_vector(0x1d, exp_29);
465 set_vector(0x1e, exp_30);
466 set_vector(0x1f, exp_31);
467
468
469 /* Setup interrupts */
470 set_vector(0x20, irq_0);
471 set_vector(0x21, irq_1);
472 set_vector(0x23, irq_3);
473 set_vector(0x24, irq_4);
474 set_vector(0x25, irq_5);
475 set_vector(0x26, irq_6);
476 set_vector(0x27, irq_7);
477 set_vector(0x28, irq_8);
478 set_vector(0x29, irq_9);
479 set_vector(0x2a, irq_10);
480 set_vector(0x2b, irq_11);
481 set_vector(0x2c, irq_12);
482 set_vector(0x2d, irq_13);
483 set_vector(0x2e, irq_14);
484 set_vector(0x2f, irq_15);
485 /* vectors 0x30-0x3f are reserved for irq 16-31 */
486 set_vector(0x40, syscall_entry);
487
488
489 /* Mask all interrupts */
490 outb(0xff, MASTER_PIC + IMR);
491 outb(0xff, SLAVE_PIC + IMR);
492
493 /* Master PIC */
494 outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
495 outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */
496 outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
497 outb(ICW4_PM, MASTER_PIC + ICW4);
498
499 for (i=0;i<8;i++) {
500 outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
501 }
502
503 /* Slave PIC */
504 outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
505 outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */
506 outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */
507 outb(ICW4_PM, SLAVE_PIC + ICW4);
508
509 for (i=0;i<8;i++) {
510 outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
511 }
512
513
514 /* enable cascade interrerupt */
515 outb(0xfb, MASTER_PIC + IMR);
516 outb(0xff, SLAVE_PIC + IMR);
517
518 /* It is now safe to enable interrupts */
519 enable_interrupts();
520
521 return 0;
522 }
523
524 void enable_interrupts(void)
525 {
526 asm("sti\n");
527 }
528
529 int disable_interrupts(void)
530 {
531 long flags;
532
533 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
534
535 return (flags&0x200); /* IE flags is bit 9 */
536 }
537
538
539 #ifdef CFG_RESET_GENERIC
540
541 void __attribute__ ((regparm(0))) generate_gpf(void);
542 asm(".globl generate_gpf\n"
543 "generate_gpf:\n"
544 "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
545 * exist */
546 void reset_cpu(ulong addr)
547 {
548 set_vector(13, generate_gpf); /* general protection fault handler */
549 set_vector(8, generate_gpf); /* double fault handler */
550 generate_gpf(); /* start the show */
551 }
552 #endif
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