cpu/ixp/npe/include/IxParityENAcc.h

   1 /**
   2  * @file IxParityENAcc.h
   3  *
   4  * @author Intel Corporation
   5  * @date 24 Mar 2004
   6  *
   7  * @brief This file contains the public API for the IXP400 Parity Error
   8  * Notifier access component.
   9  *
  10  * @par
  11  * IXP400 SW Release version 2.0
  12  *
  13  * -- Copyright Notice --
  14  *
  15  * @par
  16  * Copyright 2001-2005, Intel Corporation.
  17  * All rights reserved.
  18  *
  19  * @par
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  * 1. Redistributions of source code must retain the above copyright
  24  *    notice, this list of conditions and the following disclaimer.
  25  * 2. Redistributions in binary form must reproduce the above copyright
  26  *    notice, this list of conditions and the following disclaimer in the
  27  *    documentation and/or other materials provided with the distribution.
  28  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  29  *    may be used to endorse or promote products derived from this software
  30  *    without specific prior written permission.
  31  *
  32  * @par
  33  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  34  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  35  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  36  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  37  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  38  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  39  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  40  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  41  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  42  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  43  * SUCH DAMAGE.
  44  *
  45  * @par
  46  * -- End of Copyright Notice --
  47  */
  48
  49 /**
  50  * @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API
  51  *
  52  * @brief The public API for the Parity Error Notifier
  53  *
  54  * @{
  55  */
  56
  57 #ifndef IXPARITYENACC_H
  58 #define IXPARITYENACC_H
  59
  60 #ifdef __ixp46X
  61
  62 #include "IxOsal.h"
  63
  64 /*
  65  * #defines for function return types, etc.
  66  */
  67
  68 /**
  69  * @ingroup IxParityENAcc
  70  *
  71  * @enum IxParityENAccStatus
  72  *
  73  * @brief The status as returend from the API
  74  */
  75 typedef enum /**< IxParityENAccStatus */
  76 {
  77   IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */
  78   IX_PARITYENACC_INVALID_PARAMETERS,   /**< Invalid or NULL parameters passed */
  79   IX_PARITYENACC_NOT_INITIALISED,      /**< Access layer has not been initialised before accessing the APIs */
  80   IX_PARITYENACC_ALREADY_INITIALISED,  /**< Access layer has already been initialised */
  81   IX_PARITYENACC_OPERATION_FAILED,     /**< Operation did not succeed due to hardware failure */
  82   IX_PARITYENACC_NO_PARITY             /**< No parity condition exits or has already been cleared */
  83 } IxParityENAccStatus;
  84
  85 /**
  86  * @ingroup IxParityENAcc
  87  *
  88  * @enum IxParityENAccParityType
  89  *
  90  * @brief Odd or Even Parity Type
  91  */
  92 typedef enum  /**< IxParityENAccParityType */
  93 {
  94   IX_PARITYENACC_EVEN_PARITY,    /**< Even Parity */
  95   IX_PARITYENACC_ODD_PARITY      /**< Odd Parity */
  96 } IxParityENAccParityType;
  97
  98 /**
  99  * @ingroup IxParityENAcc
 100  *
 101  * @enum IxParityENAccConfigOption
 102  *
 103  * @brief The parity error enable/disable configuration option
 104  */
 105 typedef enum /**< IxParityENAccConfigOption */
 106 {
 107   IX_PARITYENACC_DISABLE,       /**< Disable parity error detection */
 108   IX_PARITYENACC_ENABLE         /**< Enable parity error detection */
 109 } IxParityENAccConfigOption;
 110
 111 /**
 112  * @ingroup IxParityENAcc
 113  *
 114  * @struct IxParityENAccNpeConfig
 115  *
 116  * @brief NPE parity detection is to be enabled/disabled
 117  */
 118 typedef struct /**< IxParityENAccNpeConfig */
 119 {
 120   IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */
 121   IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
 122 } IxParityENAccNpeConfig ;
 123
 124
 125 /**
 126  * @ingroup IxParityENAcc
 127  *
 128  * @struct IxParityENAccMcuConfig
 129  *
 130  * @brief MCU pairty detection is to be enabled/disabled
 131  */
 132 typedef struct /**< IxParityENAccMcuConfig */
 133 {
 134   IxParityENAccConfigOption singlebitDetectEnabled;      /**< Single-bit parity error detection */
 135   IxParityENAccConfigOption singlebitCorrectionEnabled;  /**< Single-bit parity error correction */
 136   IxParityENAccConfigOption multibitDetectionEnabled;    /**< Multi-bit  parity error detection */
 137 } IxParityENAccMcuConfig ;
 138
 139
 140 /**
 141  * @ingroup IxParityENAcc
 142  *
 143  * @struct IxParityENAccEbcConfig
 144  *
 145  * @brief Expansion Bus Controller parity detection is to be enabled or disabled
 146  *
 147  * Note: All the Chip Select(s) and External Masters will have the same parity
 148  */
 149 typedef struct /**< IxParityENAccEbcConfig */
 150 {
 151   IxParityENAccConfigOption ebcCs0Enabled;    /**< Expansion Bus Controller - Chip Select 0 */
 152   IxParityENAccConfigOption ebcCs1Enabled;    /**< Expansion Bus Controller - Chip Select 1 */
 153   IxParityENAccConfigOption ebcCs2Enabled;    /**< Expansion Bus Controller - Chip Select 2 */
 154   IxParityENAccConfigOption ebcCs3Enabled;    /**< Expansion Bus Controller - Chip Select 3 */
 155   IxParityENAccConfigOption ebcCs4Enabled;    /**< Expansion Bus Controller - Chip Select 4 */
 156   IxParityENAccConfigOption ebcCs5Enabled;    /**< Expansion Bus Controller - Chip Select 5 */
 157   IxParityENAccConfigOption ebcCs6Enabled;    /**< Expansion Bus Controller - Chip Select 6 */
 158   IxParityENAccConfigOption ebcCs7Enabled;    /**< Expansion Bus Controller - Chip Select 7 */
 159   IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */
 160   IxParityENAccParityType parityOddEven;      /**< Parity - Odd or Even */
 161 } IxParityENAccEbcConfig ;
 162
 163 /**
 164  * @ingroup IxParityENAcc
 165  *
 166  * @struct IxParityENAccHWParityConfig
 167  *
 168  * @brief Parity error configuration of the Hardware Blocks
 169  */
 170 typedef struct /**< IxParityENAccHWParityConfig */
 171 {
 172   IxParityENAccNpeConfig npeAConfig;     /**< NPE A parity detection is to be enabled/disabled */
 173   IxParityENAccNpeConfig npeBConfig;     /**< NPE B parity detection is to be enabled/disabled */
 174   IxParityENAccNpeConfig npeCConfig;     /**< NPE C parity detection is to be enabled/disabled */
 175   IxParityENAccMcuConfig mcuConfig;      /**< MCU pairty detection is to be enabled/disabled */
 176   IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */
 177   IxParityENAccConfigOption aqmEnabled;  /**< AQM parity detection is to be enabled */
 178   IxParityENAccEbcConfig ebcConfig;      /**< Expansion Bus Controller parity detection is to be enabled/disabled */
 179 } IxParityENAccHWParityConfig;
 180
 181
 182 /**
 183  * @ingroup IxParityENAcc
 184  *
 185  * @struct IxParityENAccNpeParityErrorStats
 186  *
 187  * @brief NPE parity error statistics
 188  */
 189 typedef struct  /* IxParityENAccNpeParityErrorStats */
 190 {
 191   UINT32 parityErrorsIMem;         /**< Parity errors in Instruction Memory */
 192   UINT32 parityErrorsDMem;         /**< Parity errors in Data Memory */
 193   UINT32 parityErrorsExternal;     /**< Parity errors in NPE External Entities */
 194 } IxParityENAccNpeParityErrorStats;
 195
 196 /**
 197  * @ingroup IxParityENAcc
 198  *
 199  * @struct IxParityENAccMcuParityErrorStats
 200  *
 201  * @brief DDR Memory Control Unit parity error statistics
 202  *
 203  * Note: There could be two outstanding parity errors at any given time whose address
 204  * details captured. If there is no room for the new interrupt then it would be treated
 205  * as overflow parity condition.
 206  */
 207 typedef struct  /* IxParityENAccMcuParityErrorStats */
 208 {
 209   UINT32 parityErrorsSingleBit;    /**< Parity errors of the type Single-Bit */
 210   UINT32 parityErrorsMultiBit;     /**< Parity errors of the type Multi-Bit */
 211   UINT32 parityErrorsOverflow;     /**< Parity errors when more than two parity errors occured */
 212 } IxParityENAccMcuParityErrorStats;
 213
 214 /**
 215  * @ingroup IxParityENAcc
 216  *
 217  * @struct IxParityENAccEbcParityErrorStats
 218  *
 219  * @brief Expansion Bus Controller parity error statistics
 220  */
 221 typedef struct  /* IxParityENAccEbcParityErrorStats */
 222 {
 223   UINT32 parityErrorsInbound;      /**< Odd bit parity errors on inbound transfers */
 224   UINT32 parityErrorsOutbound;     /**< Odd bit parity errors on outbound transfers */
 225 } IxParityENAccEbcParityErrorStats;
 226
 227
 228 /**
 229  * @ingroup IxParityENAcc
 230  *
 231  * @struct IxParityENAccParityErrorStats
 232  *
 233  * @brief Parity Error Statistics for the all the hardware blocks
 234  */
 235 typedef struct  /**< IxParityENAccParityErrorStats */
 236 {
 237   IxParityENAccNpeParityErrorStats  npeStats;  /**< NPE parity error statistics */
 238   IxParityENAccMcuParityErrorStats  mcuStats;  /**< MCU parity error statistics */
 239   IxParityENAccEbcParityErrorStats  ebcStats;  /**< EBC parity error statistics */
 240   UINT32                            swcpStats; /**< SWCP parity error statistics */
 241   UINT32                            aqmStats;  /**< AQM parity error statistics */
 242 } IxParityENAccParityErrorStats;
 243
 244
 245 /**
 246  * @ingroup IxParityENAcc
 247  *
 248  * @enum IxParityENAccParityErrorSource
 249  *
 250  * @brief The source of the parity error notification
 251  */
 252 typedef enum  /**< IxParityENAccParityErrorSource  */
 253 {
 254   IX_PARITYENACC_NPE_A_IMEM,     /**< NPE A - Instruction memory */
 255   IX_PARITYENACC_NPE_A_DMEM,     /**< NPE A - Data memory */
 256   IX_PARITYENACC_NPE_A_EXT,      /**< NPE A - External Entity*/
 257   IX_PARITYENACC_NPE_B_IMEM,     /**< NPE B - Instruction memory */
 258   IX_PARITYENACC_NPE_B_DMEM,     /**< NPE B - Data memory */
 259   IX_PARITYENACC_NPE_B_EXT,      /**< NPE B - External Entity*/
 260   IX_PARITYENACC_NPE_C_IMEM,     /**< NPE C - Instruction memory */
 261   IX_PARITYENACC_NPE_C_DMEM,     /**< NPE C - Data memory */
 262   IX_PARITYENACC_NPE_C_EXT,      /**< NPE C - External Entity*/
 263   IX_PARITYENACC_SWCP,           /**< SWCP */
 264   IX_PARITYENACC_AQM,            /**< AQM */
 265   IX_PARITYENACC_MCU_SBIT,       /**< DDR Memory Controller Unit - Single bit parity */
 266   IX_PARITYENACC_MCU_MBIT,       /**< DDR Memory Controller Unit - Multi bit parity */
 267   IX_PARITYENACC_MCU_OVERFLOW,   /**< DDR Memory Controller Unit - Parity errors in excess of two */
 268   IX_PARITYENACC_EBC_CS,         /**< Expansion Bus Controller - Chip Select */
 269   IX_PARITYENACC_EBC_EXTMST      /**< Expansion Bus Controller - External Master */
 270 } IxParityENAccParityErrorSource;
 271
 272 /**
 273  * @ingroup IxParityENAcc
 274  *
 275  * @enum IxParityENAccParityErrorAccess
 276  *
 277  * @brief The type of access resulting in parity error
 278  */
 279 typedef enum  /**< IxParityENAccParityErrorAccess  */
 280 {
 281   IX_PARITYENACC_READ,   /**< Read Access  */
 282   IX_PARITYENACC_WRITE   /**< Write Access */
 283 } IxParityENAccParityErrorAccess;
 284
 285 /**
 286  * @ingroup IxParityENAcc
 287  *
 288  * @typedef IxParityENAccParityErrorAddress
 289  *
 290  * @brief The memory location which has parity error
 291  */
 292 typedef UINT32 IxParityENAccParityErrorAddress;
 293
 294 /**
 295  * @ingroup IxParityENAcc
 296  *
 297  * @typedef IxParityENAccParityErrorData
 298  *
 299  * @brief The data read from the memory location which has parity error
 300  */
 301 typedef UINT32 IxParityENAccParityErrorData;
 302
 303 /**
 304  * @ingroup IxParityENAcc
 305  *
 306  * @enum IxParityENAccParityErrorRequester
 307  *
 308  * @brief The requester interface through which the SDRAM memory access
 309  * resulted in the parity error.
 310  */
 311 typedef enum  /**< IxParityENAccParityErrorRequester  */
 312 {
 313   IX_PARITYENACC_MPI,     /**< Direct Memory Port Interface  */
 314   IX_PARITYENACC_AHB_BUS  /**< South or North AHB Bus */
 315 } IxParityENAccParityErrorRequester;
 316
 317 /**
 318  * @ingroup IxParityENAcc
 319  *
 320  * @enum IxParityENAccAHBErrorMaster
 321  *
 322  * @brief The Master on the AHB bus interface whose transaction might have
 323  * resulted in the parity error notification to XScale.
 324  */
 325 typedef enum  /**< IxParityENAccAHBErrorMaster */
 326 {
 327   IX_PARITYENACC_AHBN_MST_NPE_A,       /**< NPE - A */
 328   IX_PARITYENACC_AHBN_MST_NPE_B,       /**< NPE - B */
 329   IX_PARITYENACC_AHBN_MST_NPE_C,       /**< NPE - C */
 330   IX_PARITYENACC_AHBS_MST_XSCALE,      /**< XScale Bus Interface Unit */
 331   IX_PARITYENACC_AHBS_MST_PBC,         /**< PCI Bus Controller */
 332   IX_PARITYENACC_AHBS_MST_EBC,         /**< Expansion Bus Controller */
 333   IX_PARITYENACC_AHBS_MST_AHB_BRIDGE,  /**< AHB Bridge */
 334   IX_PARITYENACC_AHBS_MST_USBH         /**< USB Host Controller */
 335 } IxParityENAccAHBErrorMaster;
 336
 337 /**
 338  * @ingroup IxParityENAcc
 339  *
 340  * @enum IxParityENAccAHBErrorSlave
 341  *
 342  * @brief The Slave on the AHB bus interface whose transaction might have
 343  * resulted in the parity error notification to XScale.
 344  */
 345 typedef enum  /**< IxParityENAccAHBErrorSlave */
 346 {
 347   IX_PARITYENACC_AHBN_SLV_MCU,         /**< Memory Control Unit */
 348   IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE,  /**< AHB Bridge */
 349   IX_PARITYENACC_AHBS_SLV_MCU,         /**< XScale Bus Interface Unit */
 350   IX_PARITYENACC_AHBS_SLV_APB_BRIDGE,  /**< APB Bridge */
 351   IX_PARITYENACC_AHBS_SLV_AQM,         /**< AQM */
 352   IX_PARITYENACC_AHBS_SLV_RSA,         /**< RSA (Crypto Bus) */
 353   IX_PARITYENACC_AHBS_SLV_PBC,         /**< PCI Bus Controller */
 354   IX_PARITYENACC_AHBS_SLV_EBC,         /**< Expansion Bus Controller */
 355   IX_PARITYENACC_AHBS_SLV_USBH         /**< USB Host Controller */
 356 } IxParityENAccAHBErrorSlave;
 357
 358 /**
 359  * @ingroup IxParityENAcc
 360  *
 361  * @struct IxParityENAccAHBErrorTransaction
 362  *
 363  * @brief The Master and Slave on the AHB bus interface whose transaction might
 364  * have resulted in the parity error notification to XScale.
 365  *
 366  * NOTE: This information may be used in the data abort exception handler
 367  * to differentiate between the XScale and non-XScale access to the SDRAM
 368  * memory.
 369  */
 370 typedef struct  /**< IxParityENAccAHBErrorTransaction  */
 371 {
 372   IxParityENAccAHBErrorMaster  ahbErrorMaster; /**< Master on AHB bus */
 373   IxParityENAccAHBErrorSlave   ahbErrorSlave;  /**< Slave  on AHB bus */
 374 } IxParityENAccAHBErrorTransaction;
 375
 376 /**
 377  * @ingroup IxParityENAcc
 378  *
 379  * @struct IxParityENAccParityErrorContextMessage
 380  *
 381  * @brief Parity Error Context Message
 382  */
 383 typedef struct /**< IxParityENAccParityErrorContextMessage */
 384 {
 385   IxParityENAccParityErrorSource     pecParitySource; /**< Source info of parity error */
 386   IxParityENAccParityErrorAccess     pecAccessType;   /**< Read or Write Access
 387                                                            Read  - NPE, SWCP, AQM, DDR MCU,
 388                                                                    Exp Bus Ctrlr (Outbound)
 389                                                            Write - DDR MCU,
 390                                                                    Exp Bus Ctrlr (Inbound
 391                                                                    i.e., External Master) */
 392   IxParityENAccParityErrorAddress    pecAddress;      /**< Address faulty location
 393                                                            Valid only for AQM, DDR MCU,
 394                                                            Exp Bus Ctrlr */
 395   IxParityENAccParityErrorData       pecData;         /**< Data read from the faulty location
 396                                                            Valid only for AQM and DDR MCU
 397                                                            For DDR MCU it is the bit location
 398                                                            of the Single-bit parity */
 399   IxParityENAccParityErrorRequester  pecRequester;    /**< Requester of SDRAM memory access
 400                                                            Valid only for the DDR MCU */
 401   IxParityENAccAHBErrorTransaction   ahbErrorTran;    /**< Master and Slave information on the
 402                                                            last AHB Error Transaction */
 403 } IxParityENAccParityErrorContextMessage;
 404
 405 /**
 406  * @ingroup IxParityENAcc
 407  *
 408  * @typedef IxParityENAccCallback
 409  *
 410  * @brief This prototype shows the format of a callback function.
 411  *
 412  * The callback will be used to notify the parity error to the client application.
 413  * The callback will be registered  by @ref ixParityENAccCallbackRegister.
 414  *
 415  * It will be called from an ISR when a parity error is detected and thus
 416  * needs to follow the interrupt callable function conventions.
 417  *
 418  */
 419 typedef void (*IxParityENAccCallback) (void);
 420
 421
 422 /*
 423  * Prototypes for interface functions.
 424  */
 425
 426 /**
 427  * @ingroup IxParityENAcc
 428  *
 429  * @fn IxParityENAccStatus ixParityENAccInit(void)
 430  *
 431  * @brief This function will initialise the IxParityENAcc component.
 432  *
 433  * This function will initialise the IxParityENAcc component. It should only be
 434  * called once, prior to using the IxParityENAcc component.
 435  *
 436  * <OL><LI>It initialises the internal data structures, registers the ISR that
 437  * will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL>
 438  *
 439  * @li Re-entrant   : No
 440  * @li ISR Callable : No
 441  *
 442  * @return @li IX_PARITYENACC_SUCCESS - Initialization is successful
 443  *         @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already
 444  *             been initialized
 445  *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
 446  *             operation didn't succeed on the hardware. Refer to error trace/log
 447  *             for details.
 448  */
 449
 450 PUBLIC IxParityENAccStatus ixParityENAccInit(void);
 451
 452 /**
 453  * @ingroup IxParityENAcc
 454  *
 455  * @fn IxParityENAccStatus ixParityENAccCallbackRegister (
 456            IxParityENAccCallback parityErrNfyCallBack)
 457  *
 458  * @brief This function will register a new callback with IxParityENAcc component.
 459  * It can also reregister a new callback replacing the old callback.
 460  *
 461  * @param parityErrNfyCallBack [in] - This parameter will specify the call-back
 462  * function supplied by the client application.
 463  *
 464  * This interface registers the user application supplied call-back handler with
 465  * the parity error handling access component after the init.
 466  *
 467  * The callback function will be called from an ISR that will be triggered by the
 468  * parity error in the IXP400 silicon.
 469  *
 470  * The following actions will be performed by this function:
 471  * <OL><LI>Check for the prior initialisation of the module before registering or
 472  * re-registering of the callback.
 473  * Check for parity error detection disabled before re-registration of the callback.
 474  * </LI></OL>
 475  *
 476  * @li   Re-entrant   : No
 477  * @li   ISR Callable : No
 478  *
 479  * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
 480  *             registration is successful.
 481  *         @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL
 482  *             parameter passed.
 483  *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
 484  *             parity error detection not yet disabled.
 485  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
 486  *             the initialisation of the access layer.
 487  */
 488
 489 PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister (
 490            IxParityENAccCallback parityErrNfyCallBack);
 491
 492 /**
 493  * @ingroup IxParityENAcc
 494  *
 495  * @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure (
 496            const IxParityENAccHWParityConfig *hwParityConfig)
 497  *
 498  * @brief This interface allows the client application to enable the parity
 499  * error detection on the underlying hardware block.
 500  *
 501  * @param hwParityConfig [in] - Hardware blocks for which the parity error
 502  * detection is to be enabled or disabled.
 503  *
 504  * The client application allocates and provides the reference to the buffer.
 505  *
 506  * It will also verify whether the specific hardware block is functional or not.
 507  *
 508  * NOTE: Failure in enabling or disabling of one or more components result in
 509  * trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function
 510  * @ref ixParityENAccParityDetectionQuery on how to verify the failures while
 511  * enabling/disabling paritys error detection.
 512  *
 513  * It shall be invoked after the Init and CallbackRegister functions but before
 514  * any other function of the IxParityENAcc layer.
 515  *
 516  * @li   Re-entrant   : No
 517  * @li   ISR Callable : No
 518  *
 519  * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
 520  *             request to enable/disable is successful.
 521  *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
 522  *             NULL parameter supplied.
 523  *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
 524  *             operation didn't succeed on the hardware.
 525  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
 526  *             the initialisation of the access layer.
 527  */
 528
 529 PUBLIC IxParityENAccStatus ixParityENAccParityDetectionConfigure (
 530            const IxParityENAccHWParityConfig *hwParityConfig);
 531
 532 /**
 533  * @ingroup IxParityENAcc
 534  *
 535  * @fn IxParityENAccStatus ixParityENAccParityDetectionQuery (
 536            IxParityENAccHWParityConfig * const hwParityConfig)
 537  *
 538  * @brief This interface allows the client application to determine the
 539  * status of the parity error detection on the specified hardware blocks
 540  *
 541  * @param hwParityConfig [out] - Hardware blocks whose parity error detection
 542  * has been enabled or disabled.
 543  *
 544  * The client application allocates and provides the reference to the buffer.
 545  *
 546  * This interface can be used immediately after the interface @ref
 547  * ixParityENAccParityDetectionConfigure to see on which of the hardware blocks
 548  * the parity error detection has either been enabled or disabled based on the
 549  * client application request.
 550  *
 551  * @li   Re-entrant   : No
 552  * @li   ISR Callable : No
 553  *
 554  * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
 555  *             request to query on whether the hardware parity error detection
 556  *             is enabled or disabled is successful.
 557  *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
 558  *             NULL parameter or invalid values supplied.
 559  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
 560  *             to the initialisation of the access layer.
 561  */
 562
 563 PUBLIC IxParityENAccStatus ixParityENAccParityDetectionQuery(
 564            IxParityENAccHWParityConfig * const hwParityConfig);
 565
 566 /**
 567  * @ingroup IxParityENAcc
 568  *
 569  * @fn IxParityENAccStatus ixParityENAccParityErrorContextGet(
 570            IxParityENAccParityErrorContextMessage * const pecMessage)
 571  *
 572  * @brief This interface allows the client application to determine the
 573  * status of the parity error context on hardware block for which the
 574  * current parity error interrupt triggered.
 575  *
 576  * @param pecMessage [out] - The parity error context information of the
 577  * parity interrupt currently being process.
 578  *
 579  * The client application allocates and provides the reference to the buffer.
 580  *
 581  * Refer to the data structure @ref IxParityENAccParityErrorContextMessage
 582  * for details.
 583  *
 584  * The routine will will fetch the parity error context in the following
 585  * priority, if multiple parity errors observed.
 586  *
 587  * <pre>
 588  * 0 - MCU (Multi-bit and single-bit in that order)
 589  * 1 - NPE-A
 590  * 2 - NPE-B
 591  * 3 - NPE-C
 592  * 4 - SWCP
 593  * 5 - QM
 594  * 6 - EXP
 595  *
 596  * NOTE: The information provided in the @ref IxParityENAccAHBErrorTransaction
 597  * may be of help for the client application to decide on the course of action
 598  * to take. This info is taken from the Performance Monitoring Unit register
 599  * which records most recent error observed on the AHB bus. This information
 600  * might have been overwritten by some other error by the time it is retrieved.
 601  * </pre>
 602  *
 603  * @li   Re-entrant   : No
 604  * @li   ISR Callable : Yes
 605  *
 606  * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
 607  *             request to get the parity error context information is successful.
 608  *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
 609  *             NULL parameter is passed
 610  *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
 611  *             the operation didn't succeed on the hardware.
 612  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
 613  *             to the initialisation of the access layer.
 614  *         @li IX_PARITYENACC_NO_PARITY - No parity condition exits or has
 615  *             already been cleared
 616  */
 617
 618 PUBLIC IxParityENAccStatus ixParityENAccParityErrorContextGet(
 619            IxParityENAccParityErrorContextMessage * const pecMessage);
 620
 621 /**
 622  * @ingroup IxParityENAcc
 623  *
 624  * @fn IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
 625           const IxParityENAccParityErrorContextMessage *pecMessage)
 626  *
 627  * @brief This interface helps the client application to clear off the
 628  * interrupt condition on the hardware block identified in the parity
 629  * error context message.  Please refer to the table below as the operation
 630  * varies depending on the interrupt source.
 631  *
 632  * @param pecMessage [in] - The parity error context information of the
 633  * hardware block whose parity error interrupt condition is to disabled.
 634  *
 635  * The client application allocates and provides the reference to the buffer.
 636  *
 637  * <pre>
 638  * ****************************************************************************
 639  * Following actions will be taken during the interrupt clear for respective
 640  * hardware blocks.
 641  *
 642  *  Parity Source     Actions taken during Interrupt clear
 643  *  -------------     -------------------------------------------------------
 644  *  NPE-A             Interrupt will be masked off at the interrupt controller
 645  *                    so that it will not trigger continuously.
 646  *                      Client application has to take appropriate action and
 647  *                      re-configure the parity error detection subsequently.
 648  *                      The client application will not be notified of further
 649  *                      interrupts, until the re-configuration is done using
 650  *                      @ref ixParityENAccParityDetectionConfigure.
 651  *
 652  *  NPE-B             Interrupt will be masked off at the interrupt controller
 653  *                    so that it will not trigger continuously.
 654  *                      Client application has to take appropriate action and
 655  *                      re-configure the parity error detection subsequently.
 656  *                      The client application will not be notified of further
 657  *                      interrupts, until the re-configuration is done using
 658  *                      @ref ixParityENAccParityDetectionConfigure.
 659  *
 660  *  NPE-C             Interrupt will be masked off at the interrupt controller
 661  *                      Client application has to take appropriate action and
 662  *                      re-configure the parity error detection subsequently.
 663  *                      The client application will not be notified of further
 664  *                      interrupts, until the re-configuration is done using
 665  *                      @ref ixParityENAccParityDetectionConfigure.
 666  *
 667  *  SWCP              Interrupt will be masked off at the interrupt controller.
 668  *                      Client application has to take appropriate action and
 669  *                      re-configure the parity error detection subsequently.
 670  *                      The client application will not be notified of further
 671  *                      interrupts, until the re-configuration is done using
 672  *                      @ref ixParityENAccParityDetectionConfigure.
 673  *
 674  *  AQM               Interrupt will be masked off at the interrupt controller.
 675  *                         Client application has to take appropriate action and
 676  *                         re-configure the parity error detection subsequently.
 677  *                         The client application will not be notified of further
 678  *                         interrupts, until the re-configuration is done using
 679  *                         @ref ixParityENAccParityDetectionConfigure.
 680  *
 681  *  MCU               Parity interrupt condition is cleared at the SDRAM MCU for
 682  *                    the following:
 683  *                    1. Single-bit
 684  *                    2. Multi-bit
 685  *                    3. Overflow condition i.e., more than two parity conditions
 686  *                       occurred
 687  *                    Note that single-parity errors do not result in data abort
 688  *                    and not all data aborts caused by multi-bit parity error.
 689  *
 690  *  EXP               Parity interrupt condition is cleared at the expansion bus
 691  *                    controller for the following:
 692  *                    1. External master initiated Inbound write
 693  *                    2. Internal master (IXP400) initiated Outbound read
 694  * ****************************************************************************
 695  * </pre>
 696  * @li   Re-entrant   : No
 697  * @li   ISR Callable : No
 698  *
 699  * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the request
 700  *             to clear the parity error interrupt condition is successful.
 701  *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
 702  *             NULL parameters have been passed or contents have been
 703  *             supplied with invalid values.
 704  *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
 705  *             the operation didn't succeed on the hardware.
 706  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
 707  *             to the initialisation of the access layer.
 708  */
 709
 710 PUBLIC IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
 711           const IxParityENAccParityErrorContextMessage *pecMessage);
 712
 713 /**
 714  * @ingroup IxParityENAcc
 715  *
 716  * @fn IxParityENAccStatus ixParityENAccStatsGet (
 717             IxParityENAccParityErrorStats * const ixParityErrorStats)
 718  *
 719  * @brief This interface allows the client application to retrieve parity
 720  * error statistics for all the hardware blocks
 721  *
 722  * @param ixParityErrorStats - [out] The statistics for all the hardware blocks.
 723  *
 724  * The client application allocates and provides the reference to the buffer.
 725  *
 726  * @li   Re-entrant   : No
 727  * @li   ISR Callable : Yes
 728  *
 729  * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
 730  *             request to retrieve parity error statistics for the hardware
 731  *             block is successful.
 732  *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to a
 733  *             NULL parameter passed.
 734  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
 735  *             to the initialisation of the access layer.
 736  */
 737
 738 PUBLIC IxParityENAccStatus ixParityENAccStatsGet (
 739             IxParityENAccParityErrorStats * const ixParityErrorStats);
 740
 741 /**
 742  * @ingroup IxParityENAcc
 743  *
 744  * @fn IxParityENAccStatus ixParityENAccStatsShow (void)
 745  *
 746  * @brief This interface allows the client application to print all the
 747  * parity error statistics.
 748  *
 749  * @li   Re-entrant   : No
 750  * @li   ISR Callable : No
 751  *
 752  * @return @li IX_PARITYENACC_SUCCESS - The request to show the pairty
 753  *             error statistics is successful.
 754  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
 755  *             prior to the initialisation of the access layer.
 756  */
 757
 758 PUBLIC IxParityENAccStatus ixParityENAccStatsShow (void);
 759
 760 /**
 761  * @ingroup IxParityENAcc
 762  *
 763  * @fn IxParityENAccStatus ixParityENAccStatsReset (void)
 764  *
 765  * @brief This interface allows the client application to reset all the
 766  * parity error statistics.
 767  *
 768  * @li   Re-entrant   : No
 769  * @li   ISR Callable : No
 770  *
 771  * @return @li IX_PARITYENACC_SUCCESS - The request to reset the parity
 772  *             error statistics is successful.
 773  *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
 774  *             prior to the initialisation of the access layer.
 775  */
 776
 777 PUBLIC IxParityENAccStatus ixParityENAccStatsReset (void);
 778
 779 #endif /* IXPARITYENACC_H */
 780 #endif /* __ixp46X */
 781
 782 /**
 783  * @} defgroup IxParityENAcc
 784  */
 785