cpu/ixp/start.S

   1 /* vi: set ts=8 sw=8 noet: */
   2 /*
   3  *  u-boot - Startup Code for XScale IXP
   4  *
   5  * Copyright (C) 2003   Kyle Harris <kharris@nexus-tech.net>
   6  *
   7  * Based on startup code example contained in the
   8  * Intel IXP4xx Programmer's Guide and past u-boot Start.S
   9  * samples.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/arch/ixp425.h>
  33
  34 #define MMU_Control_M  0x001    /* Enable MMU */
  35 #define MMU_Control_A  0x002    /* Enable address alignment faults */
  36 #define MMU_Control_C  0x004    /* Enable cache */
  37 #define MMU_Control_W  0x008    /* Enable write-buffer */
  38 #define MMU_Control_P  0x010    /* Compatability: 32 bit code */
  39 #define MMU_Control_D  0x020    /* Compatability: 32 bit data */
  40 #define MMU_Control_L  0x040    /* Compatability: */
  41 #define MMU_Control_B  0x080    /* Enable Big-Endian */
  42 #define MMU_Control_S  0x100    /* Enable system protection */
  43 #define MMU_Control_R  0x200    /* Enable ROM protection */
  44 #define MMU_Control_I  0x1000   /* Enable Instruction cache */
  45 #define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
  46 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  47
  48
  49 /*
  50  * Macro definitions
  51  */
  52         /* Delay a bit */
  53         .macro DELAY_FOR cycles, reg0
  54         ldr     \reg0, =\cycles
  55         subs    \reg0, \reg0, #1
  56         subne   pc,  pc, #0xc
  57         .endm
  58
  59         /* wait for coprocessor write complete */
  60         .macro CPWAIT reg
  61         mrc  p15,0,\reg,c2,c0,0
  62         mov  \reg,\reg
  63         sub  pc,pc,#4
  64         .endm
  65
  66 .globl _start
  67 _start: b       reset
  68         ldr     pc, _undefined_instruction
  69         ldr     pc, _software_interrupt
  70         ldr     pc, _prefetch_abort
  71         ldr     pc, _data_abort
  72         ldr     pc, _not_used
  73         ldr     pc, _irq
  74         ldr     pc, _fiq
  75
  76 _undefined_instruction: .word undefined_instruction
  77 _software_interrupt:    .word software_interrupt
  78 _prefetch_abort:        .word prefetch_abort
  79 _data_abort:            .word data_abort
  80 _not_used:              .word not_used
  81 _irq:                   .word irq
  82 _fiq:                   .word fiq
  83
  84         .balignl 16,0xdeadbeef
  85
  86
  87 /*
  88  * Startup Code (reset vector)
  89  *
  90  * do important init only if we don't start from memory!
  91  * - relocate armboot to ram
  92  * - setup stack
  93  * - jump to second stage
  94  */
  95
  96 _TEXT_BASE:
  97         .word   TEXT_BASE
  98
  99 .globl _armboot_start
 100 _armboot_start:
 101         .word _start
 102
 103 /*
 104  * Note: _armboot_end_data and _armboot_end are defined
 105  * by the (board-dependent) linker script.
 106  * _armboot_end_data is the first usable FLASH address after armboot
 107  */
 108 .globl _armboot_end_data
 109 _armboot_end_data:
 110         .word armboot_end_data
 111 .globl _armboot_end
 112 _armboot_end:
 113         .word armboot_end
 114
 115 /*
 116  * This is defined in the board specific linker script
 117  */
 118 .globl _bss_start
 119 _bss_start:
 120         .word bss_start
 121
 122 .globl _bss_end
 123 _bss_end:
 124         .word bss_end
 125
 126 /*
 127  * _armboot_real_end is the first usable RAM address behind armboot
 128  * and the various stacks
 129  */
 130 .globl _armboot_real_end
 131 _armboot_real_end:
 132         .word 0x0badc0de
 133
 134 /*
 135  * We relocate uboot to this address (end of RAM - 128 KiB)
 136  */
 137 .globl _uboot_reloc
 138 _uboot_reloc:
 139         .word TEXT_BASE
 140
 141 #ifdef CONFIG_USE_IRQ
 142 /* IRQ stack memory (calculated at run-time) */
 143 .globl IRQ_STACK_START
 144 IRQ_STACK_START:
 145         .word   0x0badc0de
 146
 147 /* IRQ stack memory (calculated at run-time) */
 148 .globl FIQ_STACK_START
 149 FIQ_STACK_START:
 150         .word 0x0badc0de
 151 #endif
 152
 153 /****************************************************************************/
 154 /*                                                                          */
 155 /* the actual reset code                                                    */
 156 /*                                                                          */
 157 /****************************************************************************/
 158
 159 reset:
 160         /* disable mmu, set big-endian */
 161         mov     r0, #0xf8
 162         mcr     p15, 0, r0, c1, c0, 0
 163         CPWAIT  r0
 164
 165         /* invalidate I & D caches & BTB */
 166         mcr     p15, 0, r0, c7, c7, 0
 167         CPWAIT  r0
 168
 169         /* invalidate I & Data TLB */
 170         mcr     p15, 0, r0, c8, c7, 0
 171         CPWAIT r0
 172
 173         /* drain write and fill buffers */
 174         mcr     p15, 0, r0, c7, c10, 4
 175         CPWAIT  r0
 176
 177         /* disable write buffer coalescing */
 178         mrc     p15, 0, r0, c1, c0, 1
 179         orr     r0, r0, #1
 180         mcr     p15, 0, r0, c1, c0, 1
 181         CPWAIT  r0
 182
 183         /* set EXP CS0 to the optimum timing */
 184         ldr     r1, =CFG_EXP_CS0
 185         ldr     r2, =IXP425_EXP_CS0
 186         str     r1, [r2]
 187
 188         /* make sure flash is visible at 0 */
 189         ldr     r2, =IXP425_EXP_CFG0
 190         ldr     r1, [r2]
 191         orr     r1, r1, #0x80000000
 192         str     r1, [r2]
 193
 194         mov     r1, #CFG_SDR_CONFIG
 195         ldr     r2, =IXP425_SDR_CONFIG
 196         str     r1, [r2]
 197
 198         /* disable refresh cycles */
 199         mov     r1, #0
 200         ldr     r3, =IXP425_SDR_REFRESH
 201         str     r1, [r3]
 202
 203         /* send nop command */
 204         mov     r1, #3
 205         ldr     r4, =IXP425_SDR_IR
 206         str     r1, [r4]
 207         DELAY_FOR 0x4000, r0
 208
 209         /* set SDRAM internal refresh val */
 210         ldr     r1, =CFG_SDRAM_REFRESH_CNT
 211         str     r1, [r3]
 212         DELAY_FOR 0x4000, r0
 213
 214         /* send precharge-all command to close all open banks */
 215         mov     r1, #2
 216         str     r1, [r4]
 217         DELAY_FOR 0x4000, r0
 218
 219         /* provide 8 auto-refresh cycles */
 220         mov     r1, #4
 221         mov     r5, #8
 222 111:    str     r1, [r4]
 223         DELAY_FOR 0x100, r0
 224         subs    r5, r5, #1
 225         bne     111b
 226
 227         /* set mode register in sdram */
 228         mov     r1, #1
 229         str     r1, [r4]
 230         DELAY_FOR 0x4000, r0
 231
 232         /* send normal operation command */
 233         mov     r1, #6
 234         str     r1, [r4]
 235         DELAY_FOR 0x4000, r0
 236
 237         /* copy */
 238         mov     r0, #0
 239         mov     r4, r0
 240         add     r2, r0, #0x40000
 241         mov     r1, #0x10000000
 242         mov     r5, r1
 243
 244     30:
 245         ldr     r3, [r0], #4
 246         str     r3, [r1], #4
 247         cmp     r0, r2
 248         bne     30b
 249
 250         /* invalidate I & D caches & BTB */
 251         mcr     p15, 0, r0, c7, c7, 0
 252         CPWAIT  r0
 253
 254         /* invalidate I & Data TLB */
 255         mcr     p15, 0, r0, c8, c7, 0
 256         CPWAIT r0
 257
 258         /* drain write and fill buffers */
 259         mcr     p15, 0, r0, c7, c10, 4
 260         CPWAIT  r0
 261
 262         /* move flash to 0x50000000 */
 263         ldr     r2, =IXP425_EXP_CFG0
 264         ldr     r1, [r2]
 265         bic     r1, r1, #0x80000000
 266         str     r1, [r2]
 267
 268         nop
 269         nop
 270         nop
 271         nop
 272         nop
 273         nop
 274
 275         /* invalidate I & Data TLB */
 276         mcr     p15, 0, r0, c8, c7, 0
 277         CPWAIT r0
 278
 279         /* enable I cache */
 280         mrc     p15, 0, r0, c1, c0, 0
 281         orr     r0, r0, #MMU_Control_I
 282         mcr     p15, 0, r0, c1, c0, 0
 283         CPWAIT  r0
 284
 285         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 286         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 287         orr     r0,r0,#0x13
 288         msr     cpsr,r0
 289
 290 relocate:                               /* relocate U-Boot to RAM           */
 291         adr     r0, _start              /* r0 <- current position of code   */
 292         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 293         cmp     r0, r1                  /* don't reloc during debug         */
 294         beq     stack_setup
 295
 296         ldr     r2, _armboot_start
 297         ldr     r3, _armboot_end
 298         sub     r2, r3, r2              /* r2 <- size of armboot            */
 299         add     r2, r0, r2              /* r2 <- source end address         */
 300
 301 copy_loop:
 302         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 303         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 304         cmp     r0, r2                  /* until source end addreee [r2]    */
 305         ble     copy_loop
 306
 307         /* Set up the stack                                                 */
 308
 309 stack_setup:
 310
 311         ldr     r0, _uboot_reloc        /* upper 128 KiB: relocated uboot   */
 312         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 313                                         /* FIXME: bdinfo should be here     */
 314         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 315
 316 clear_bss:
 317
 318         ldr     r0, _bss_start          /* find start of bss segment        */
 319         add     r0, r0, #4              /* start at first byte of bss       */
 320         ldr     r1, _bss_end            /* stop here                        */
 321         mov     r2, #0x00000000         /* clear                            */
 322
 323 clbss_l:str     r2, [r0]                /* clear loop...                    */
 324         add     r0, r0, #4
 325         cmp     r0, r1
 326         bne     clbss_l
 327
 328
 329         ldr     pc, _start_armboot
 330
 331 _start_armboot: .word start_armboot
 332
 333
 334 /****************************************************************************/
 335 /*                                                                          */
 336 /* Interrupt handling                                                       */
 337 /*                                                                          */
 338 /****************************************************************************/
 339
 340 /* IRQ stack frame                                                          */
 341
 342 #define S_FRAME_SIZE    72
 343
 344 #define S_OLD_R0        68
 345 #define S_PSR           64
 346 #define S_PC            60
 347 #define S_LR            56
 348 #define S_SP            52
 349
 350 #define S_IP            48
 351 #define S_FP            44
 352 #define S_R10           40
 353 #define S_R9            36
 354 #define S_R8            32
 355 #define S_R7            28
 356 #define S_R6            24
 357 #define S_R5            20
 358 #define S_R4            16
 359 #define S_R3            12
 360 #define S_R2            8
 361 #define S_R1            4
 362 #define S_R0            0
 363
 364 #define MODE_SVC 0x13
 365
 366         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 367
 368         .macro  bad_save_user_regs
 369         sub     sp, sp, #S_FRAME_SIZE
 370         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 371         add     r8, sp, #S_PC
 372
 373         ldr     r2, _armboot_end
 374         add     r2, r2, #CONFIG_STACKSIZE
 375         sub     r2, r2, #8
 376         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 377         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 378
 379         add     r5, sp, #S_SP
 380         mov     r1, lr
 381         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 382         mov     r0, sp
 383         .endm
 384
 385
 386         /* use irq_save_user_regs / irq_restore_user_regs for                */
 387         /* IRQ/FIQ handling                                                  */
 388
 389         .macro  irq_save_user_regs
 390         sub     sp, sp, #S_FRAME_SIZE
 391         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 392         add     r8, sp, #S_PC
 393         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 394         str     lr, [r8, #0]                    /* Save calling PC           */
 395         mrs     r6, spsr
 396         str     r6, [r8, #4]                    /* Save CPSR                 */
 397         str     r0, [r8, #8]                    /* Save OLD_R0               */
 398         mov     r0, sp
 399         .endm
 400
 401         .macro  irq_restore_user_regs
 402         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 403         mov     r0, r0
 404         ldr     lr, [sp, #S_PC]                 @ Get PC
 405         add     sp, sp, #S_FRAME_SIZE
 406         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 407         .endm
 408
 409         .macro get_bad_stack
 410         ldr     r13, _armboot_end               @ setup our mode stack
 411         add     r13, r13, #CONFIG_STACKSIZE     @ resides at top of normal stack
 412         sub     r13, r13, #8
 413
 414         str     lr, [r13]                       @ save caller lr / spsr
 415         mrs     lr, spsr
 416         str     lr, [r13, #4]
 417
 418         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 419         msr     spsr_c, r13
 420         mov     lr, pc
 421         movs    pc, lr
 422         .endm
 423
 424         .macro get_irq_stack                    @ setup IRQ stack
 425         ldr     sp, IRQ_STACK_START
 426         .endm
 427
 428         .macro get_fiq_stack                    @ setup FIQ stack
 429         ldr     sp, FIQ_STACK_START
 430         .endm
 431
 432
 433 /****************************************************************************/
 434 /*                                                                          */
 435 /* exception handlers                                                       */
 436 /*                                                                          */
 437 /****************************************************************************/
 438
 439         .align  5
 440 undefined_instruction:
 441         get_bad_stack
 442         bad_save_user_regs
 443         bl      do_undefined_instruction
 444
 445         .align  5
 446 software_interrupt:
 447         get_bad_stack
 448         bad_save_user_regs
 449         bl      do_software_interrupt
 450
 451         .align  5
 452 prefetch_abort:
 453         get_bad_stack
 454         bad_save_user_regs
 455         bl      do_prefetch_abort
 456
 457         .align  5
 458 data_abort:
 459         get_bad_stack
 460         bad_save_user_regs
 461         bl      do_data_abort
 462
 463         .align  5
 464 not_used:
 465         get_bad_stack
 466         bad_save_user_regs
 467         bl      do_not_used
 468
 469 #ifdef CONFIG_USE_IRQ
 470
 471         .align  5
 472 irq:
 473         get_irq_stack
 474         irq_save_user_regs
 475         bl      do_irq
 476         irq_restore_user_regs
 477
 478         .align  5
 479 fiq:
 480         get_fiq_stack
 481         irq_save_user_regs              /* someone ought to write a more    */
 482         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 483         irq_restore_user_regs
 484
 485 #else
 486
 487         .align  5
 488 irq:
 489         get_bad_stack
 490         bad_save_user_regs
 491         bl      do_irq
 492
 493         .align  5
 494 fiq:
 495         get_bad_stack
 496         bad_save_user_regs
 497         bl      do_fiq
 498
 499 #endif
 500
 501 /****************************************************************************/
 502 /*                                                                          */
 503 /* Reset function: Use Watchdog to reset                                    */
 504 /*                                                                          */
 505 /****************************************************************************/
 506
 507         .align  5
 508 .globl reset_cpu
 509
 510 reset_cpu:
 511         ldr     r1, =0x482e
 512         ldr     r2, =IXP425_OSWK
 513         str     r1, [r2]
 514         ldr     r1, =0x0fff
 515         ldr     r2, =IXP425_OSWT
 516         str     r1, [r2]
 517         ldr     r1, =0x5
 518         ldr     r2, =IXP425_OSWE
 519         str     r1, [r2]
 520         b       reset_endless
 521
 522
 523 reset_endless:
 524
 525         b       reset_endless