cpu/lh7a40x/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /*
  29  * CPU specific code
  30  */
  31
  32 #include <common.h>
  33 #include <command.h>
  34 #include <arm920t.h>
  35
  36 /* read co-processor 15, register #1 (control register) */
  37 static unsigned long read_p15_c1 (void)
  38 {
  39         unsigned long value;
  40
  41         __asm__ __volatile__(
  42                 "mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
  43                 : "=r" (value)
  44                 :
  45                 : "memory");
  46
  47 #ifdef MMU_DEBUG
  48         printf ("p15/c1 is = %08lx\n", value);
  49 #endif
  50         return value;
  51 }
  52
  53 /* write to co-processor 15, register #1 (control register) */
  54 static void write_p15_c1 (unsigned long value)
  55 {
  56 #ifdef MMU_DEBUG
  57         printf ("write %08lx to p15/c1\n", value);
  58 #endif
  59         __asm__ __volatile__(
  60                 "mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
  61                 :
  62                 : "r" (value)
  63                 : "memory");
  64
  65         read_p15_c1 ();
  66 }
  67
  68 static void cp_delay (void)
  69 {
  70         volatile int i;
  71
  72         /* copro seems to need some delay between reading and writing */
  73         for (i = 0; i < 100; i++);
  74 }
  75
  76 /* See also ARM Ref. Man. */
  77 #define C1_MMU          (1<<0)          /* mmu off/on */
  78 #define C1_ALIGN        (1<<1)          /* alignment faults off/on */
  79 #define C1_DC           (1<<2)          /* dcache off/on */
  80 #define C1_BIG_ENDIAN   (1<<7)  /* big endian off/on */
  81 #define C1_SYS_PROT     (1<<8)          /* system protection */
  82 #define C1_ROM_PROT     (1<<9)          /* ROM protection */
  83 #define C1_IC           (1<<12)         /* icache off/on */
  84 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
  85 #define RESERVED_1      (0xf << 3)      /* must be 111b for R/W */
  86
  87 int cpu_init (void)
  88 {
  89         /*
  90          * setup up stacks if necessary
  91          */
  92 #ifdef CONFIG_USE_IRQ
  93         DECLARE_GLOBAL_DATA_PTR;
  94
  95         IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
  96         FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  97 #endif
  98         return 0;
  99 }
 100
 101 int cleanup_before_linux (void)
 102 {
 103         /*
 104          * this function is called just before we call linux
 105          * it prepares the processor for linux
 106          *
 107          * we turn off caches etc ...
 108          */
 109
 110         unsigned long i;
 111
 112         disable_interrupts ();
 113
 114         /* turn off I/D-cache */
 115         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 116         i &= ~(C1_DC | C1_IC);
 117         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 118
 119         /* flush I/D-cache */
 120         i = 0;
 121         asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 122         return (0);
 123 }
 124
 125 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 126 {
 127         disable_interrupts ();
 128         reset_cpu (0);
 129         /*NOTREACHED*/
 130         return (0);
 131 }
 132
 133 void icache_enable (void)
 134 {
 135         ulong reg;
 136
 137         reg = read_p15_c1 ();
 138         cp_delay ();
 139         write_p15_c1 (reg | C1_IC);
 140 }
 141
 142 void icache_disable (void)
 143 {
 144         ulong reg;
 145
 146         reg = read_p15_c1 ();
 147         cp_delay ();
 148         write_p15_c1 (reg & ~C1_IC);
 149 }
 150
 151 int icache_status (void)
 152 {
 153         return (read_p15_c1 () & C1_IC) != 0;
 154 }
 155
 156 #ifdef USE_920T_MMU
 157 /* It makes no sense to use the dcache if the MMU is not enabled */
 158 void dcache_enable (void)
 159 {
 160         ulong reg;
 161
 162         reg = read_p15_c1 ();
 163         cp_delay ();
 164         write_p15_c1 (reg | C1_DC);
 165 }
 166
 167 void dcache_disable (void)
 168 {
 169         ulong reg;
 170
 171         reg = read_p15_c1 ();
 172         cp_delay ();
 173         reg &= ~C1_DC;
 174         write_p15_c1 (reg);
 175 }
 176
 177 int dcache_status (void)
 178 {
 179         return (read_p15_c1 () & C1_DC) != 0;
 180 }
 181 #endif