cpu/mips/cpu.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/cacheops.h>
  28 #include <asm/reboot.h>
  29
  30 #define cache_op(op,addr)                                               \
  31         __asm__ __volatile__(                                           \
  32         "       .set    push                                    \n"     \
  33         "       .set    noreorder                               \n"     \
  34         "       .set    mips3\n\t                               \n"     \
  35         "       cache   %0, %1                                  \n"     \
  36         "       .set    pop                                     \n"     \
  37         :                                                               \
  38         : "i" (op), "R" (*(unsigned char *)(addr)))
  39
  40 void __attribute__((weak)) _machine_restart(void)
  41 {
  42 }
  43
  44 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  45 {
  46         _machine_restart();
  47
  48         fprintf(stderr, "*** reset failed ***\n");
  49         return 0;
  50 }
  51
  52 void flush_cache(ulong start_addr, ulong size)
  53 {
  54         unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
  55         unsigned long addr = start_addr & ~(lsize - 1);
  56         unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
  57
  58         while (1) {
  59                 cache_op(Hit_Writeback_Inv_D, addr);
  60                 cache_op(Hit_Invalidate_I, addr);
  61                 if (addr == aend)
  62                         break;
  63                 addr += lsize;
  64         }
  65 }
  66
  67 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
  68 {
  69         write_c0_entrylo0(low0);
  70         write_c0_pagemask(pagemask);
  71         write_c0_entrylo1(low1);
  72         write_c0_entryhi(hi);
  73         write_c0_index(index);
  74         tlb_write_indexed();
  75 }