cpu/mpc512x/start.S

   1 /*
   2  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
   5  * Copyright Freescale Semiconductor, Inc. 2004, 2006.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  *
  25  * Based on the MPC83xx code.
  26  */
  27
  28 /*
  29  *  U-Boot - Startup Code for MPC512x based Embedded Boards
  30  */
  31
  32 #include <config.h>
  33 #include <timestamp.h>
  34 #include <version.h>
  35
  36 #define CONFIG_521X     1               /* needed for Linux kernel header files*/
  37
  38 #include <asm/immap_512x.h>
  39 #include "asm-offsets.h"
  40
  41 #include <ppc_asm.tmpl>
  42 #include <ppc_defs.h>
  43
  44 #include <asm/cache.h>
  45 #include <asm/mmu.h>
  46
  47 #ifndef  CONFIG_IDENT_STRING
  48 #define  CONFIG_IDENT_STRING "MPC512X"
  49 #endif
  50
  51 /*
  52  * Floating Point enable, Machine Check and Recoverable Interr.
  53  */
  54 #undef  MSR_KERNEL
  55 #ifdef DEBUG
  56 #define MSR_KERNEL (MSR_FP|MSR_RI)
  57 #else
  58 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  59 #endif
  60
  61 /* Macros for manipulating CSx_START/STOP */
  62 #define START_REG(start)        ((start) >> 16)
  63 #define STOP_REG(start, size)   (((start) + (size) - 1) >> 16)
  64
  65 /*
  66  * Set up GOT: Global Offset Table
  67  *
  68  * Use r14 to access the GOT
  69  */
  70         START_GOT
  71         GOT_ENTRY(_GOT2_TABLE_)
  72         GOT_ENTRY(_FIXUP_TABLE_)
  73
  74         GOT_ENTRY(_start)
  75         GOT_ENTRY(_start_of_vectors)
  76         GOT_ENTRY(_end_of_vectors)
  77         GOT_ENTRY(transfer_to_handler)
  78
  79         GOT_ENTRY(__init_end)
  80         GOT_ENTRY(_end)
  81         GOT_ENTRY(__bss_start)
  82         END_GOT
  83
  84 /*
  85  * Magic number and version string
  86  */
  87         .long   0x27051956              /* U-Boot Magic Number */
  88         .globl  version_string
  89 version_string:
  90         .ascii U_BOOT_VERSION
  91         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  92         .ascii " ", CONFIG_IDENT_STRING, "\0"
  93
  94 /*
  95  * Vector Table
  96  */
  97         .text
  98         . = EXC_OFF_SYS_RESET
  99
 100         .globl  _start
 101         /* Start from here after reset/power on */
 102 _start:
 103         li      r21, BOOTFLAG_COLD  /* Normal Power-On: Boot from FLASH */
 104         b       boot_cold
 105
 106         .globl  _start_of_vectors
 107 _start_of_vectors:
 108
 109 /* Machine check */
 110         STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 111
 112 /* Data Storage exception. */
 113         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 114
 115 /* Instruction Storage exception. */
 116         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 117
 118 /* External Interrupt exception. */
 119         STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
 120
 121 /* Alignment exception. */
 122         . = 0x600
 123 Alignment:
 124         EXCEPTION_PROLOG(SRR0, SRR1)
 125         mfspr   r4,DAR
 126         stw     r4,_DAR(r21)
 127         mfspr   r5,DSISR
 128         stw     r5,_DSISR(r21)
 129         addi    r3,r1,STACK_FRAME_OVERHEAD
 130         li      r20,MSR_KERNEL
 131         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 132         rlwimi  r20,r23,0,25,25         /* copy IP bit from saved MSR */
 133         lwz     r6,GOT(transfer_to_handler)
 134         mtlr    r6
 135         blrl
 136 .L_Alignment:
 137         .long   AlignmentException - _start + EXC_OFF_SYS_RESET
 138         .long   int_return - _start + EXC_OFF_SYS_RESET
 139
 140 /* Program check exception */
 141         . = 0x700
 142 ProgramCheck:
 143         EXCEPTION_PROLOG(SRR0, SRR1)
 144         addi    r3,r1,STACK_FRAME_OVERHEAD
 145         li      r20,MSR_KERNEL
 146         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 147         rlwimi  r20,r23,0,25,25         /* copy IP bit from saved MSR */
 148         lwz     r6,GOT(transfer_to_handler)
 149         mtlr    r6
 150         blrl
 151 .L_ProgramCheck:
 152         .long   ProgramCheckException - _start + EXC_OFF_SYS_RESET
 153         .long   int_return - _start + EXC_OFF_SYS_RESET
 154
 155 /* Floating Point Unit unavailable exception */
 156         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 157
 158 /* Decrementer */
 159         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 160
 161 /* Critical interrupt */
 162         STD_EXCEPTION(0xa00, Critical, UnknownException)
 163
 164 /* System Call */
 165         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 166
 167 /* Trace interrupt */
 168         STD_EXCEPTION(0xd00, Trace, UnknownException)
 169
 170 /* Performance Monitor interrupt */
 171         STD_EXCEPTION(0xf00, PerfMon, UnknownException)
 172
 173 /* Intruction Translation Miss */
 174         STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
 175
 176 /* Data Load Translation Miss */
 177         STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
 178
 179 /* Data Store Translation Miss */
 180         STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
 181
 182 /* Instruction Address Breakpoint */
 183         STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
 184
 185 /* System Management interrupt */
 186         STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
 187
 188         .globl  _end_of_vectors
 189 _end_of_vectors:
 190
 191         . = 0x3000
 192 boot_cold:
 193         /* Save msr contents */
 194         mfmsr   r5
 195
 196         /* Set IMMR area to our preferred location */
 197         lis     r4, CONFIG_DEFAULT_IMMR@h
 198         lis     r3, CONFIG_SYS_IMMR@h
 199         ori     r3, r3, CONFIG_SYS_IMMR@l
 200         stw     r3, IMMRBAR(r4)
 201         mtspr   MBAR, r3                /* IMMRBAR is mirrored into the MBAR SPR (311) */
 202
 203         /* Initialise the machine */
 204         bl      cpu_early_init
 205
 206         /*
 207          * Set up Local Access Windows:
 208          *
 209          * 1) Boot/CS0 (boot FLASH)
 210          * 2) On-chip SRAM (initial stack purposes)
 211          */
 212
 213         /* Boot CS/CS0 window range */
 214         lis     r3, CONFIG_SYS_IMMR@h
 215         ori     r3, r3, CONFIG_SYS_IMMR@l
 216
 217         lis     r4, START_REG(CONFIG_SYS_FLASH_BASE)
 218         ori     r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
 219         stw     r4, LPCS0AW(r3)
 220
 221         /*
 222          * The SRAM window has a fixed size (256K), so only the start address
 223          * is necessary
 224          */
 225         lis     r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
 226         stw     r4, SRAMBAR(r3)
 227
 228         /*
 229          * According to MPC5121e RM, configuring local access windows should
 230          * be followed by a dummy read of the config register that was
 231          * modified last and an isync
 232          */
 233         lwz     r4, SRAMBAR(r3)
 234         isync
 235
 236         /*
 237          * Set configuration of the Boot/CS0, the SRAM window does not have a
 238          * config register so no params can be set for it
 239          */
 240         lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
 241         ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
 242
 243         lis     r4, CONFIG_SYS_CS0_CFG@h
 244         ori     r4, r4, CONFIG_SYS_CS0_CFG@l
 245         stw     r4, CS0_CONFIG(r3)
 246
 247         /* Master enable all CS's */
 248         lis     r4, CS_CTRL_ME@h
 249         ori     r4, r4, CS_CTRL_ME@l
 250         stw     r4, CS_CTRL(r3)
 251
 252         lis     r4, (CONFIG_SYS_MONITOR_BASE)@h
 253         ori     r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
 254         addi    r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
 255         mtlr    r5
 256         blr
 257
 258 in_flash:
 259         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
 260         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
 261
 262         li      r0, 0           /* Make room for stack frame header and */
 263         stwu    r0, -4(r1)      /* clear final stack frame so that      */
 264         stwu    r0, -4(r1)      /* stack backtraces terminate cleanly   */
 265
 266         /* let the C-code set up the rest                       */
 267         /*                                                      */
 268         /* Be careful to keep code relocatable & stack humble   */
 269         /*------------------------------------------------------*/
 270
 271         GET_GOT                 /* initialize GOT access        */
 272
 273         /* r3: IMMR */
 274         lis     r3, CONFIG_SYS_IMMR@h
 275         /* run low-level CPU init code (in Flash) */
 276         bl      cpu_init_f
 277
 278         /* r3: BOOTFLAG */
 279         mr      r3, r21
 280         /* run 1st part of board init code (in Flash) */
 281         bl      board_init_f
 282
 283         /* NOTREACHED - board_init_f() does not return */
 284
 285 /*
 286  * This code finishes saving the registers to the exception frame
 287  * and jumps to the appropriate handler for the exception.
 288  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 289  */
 290         .globl  transfer_to_handler
 291 transfer_to_handler:
 292         stw     r22,_NIP(r21)
 293         lis     r22,MSR_POW@h
 294         andc    r23,r23,r22
 295         stw     r23,_MSR(r21)
 296         SAVE_GPR(7, r21)
 297         SAVE_4GPRS(8, r21)
 298         SAVE_8GPRS(12, r21)
 299         SAVE_8GPRS(24, r21)
 300         mflr    r23
 301         andi.   r24,r23,0x3f00          /* get vector offset */
 302         stw     r24,TRAP(r21)
 303         li      r22,0
 304         stw     r22,RESULT(r21)
 305         lwz     r24,0(r23)              /* virtual address of handler */
 306         lwz     r23,4(r23)              /* where to go when done */
 307         mtspr   SRR0,r24
 308         mtspr   SRR1,r20
 309         mtlr    r23
 310         SYNC
 311         rfi                             /* jump to handler, enable MMU */
 312
 313 int_return:
 314         mfmsr   r28             /* Disable interrupts */
 315         li      r4,0
 316         ori     r4,r4,MSR_EE
 317         andc    r28,r28,r4
 318         SYNC                    /* Some chip revs need this... */
 319         mtmsr   r28
 320         SYNC
 321         lwz     r2,_CTR(r1)
 322         lwz     r0,_LINK(r1)
 323         mtctr   r2
 324         mtlr    r0
 325         lwz     r2,_XER(r1)
 326         lwz     r0,_CCR(r1)
 327         mtspr   XER,r2
 328         mtcrf   0xFF,r0
 329         REST_10GPRS(3, r1)
 330         REST_10GPRS(13, r1)
 331         REST_8GPRS(23, r1)
 332         REST_GPR(31, r1)
 333         lwz     r2,_NIP(r1)     /* Restore environment */
 334         lwz     r0,_MSR(r1)
 335         mtspr   SRR0,r2
 336         mtspr   SRR1,r0
 337         lwz     r0,GPR0(r1)
 338         lwz     r2,GPR2(r1)
 339         lwz     r1,GPR1(r1)
 340         SYNC
 341         rfi
 342
 343 /*
 344  * This code initialises the machine, it expects original MSR contents to be in r5.
 345  */
 346 cpu_early_init:
 347         /* Initialize machine status; enable machine check interrupt */
 348         /*-----------------------------------------------------------*/
 349
 350         li      r3, MSR_KERNEL                  /* Set ME and RI flags */
 351         rlwimi  r3, r5, 0, 25, 25               /* preserve IP bit */
 352 #ifdef DEBUG
 353         rlwimi  r3, r5, 0, 21, 22               /* debugger might set SE, BE bits */
 354 #endif
 355         mtmsr   r3
 356         SYNC
 357         mtspr   SRR1, r3                        /* Mirror current MSR state in SRR1 */
 358
 359         lis     r3, CONFIG_SYS_IMMR@h
 360
 361 #if defined(CONFIG_WATCHDOG)
 362         /* Initialise the watchdog and reset it */
 363         /*--------------------------------------*/
 364         lis r4, CONFIG_SYS_WATCHDOG_VALUE
 365         ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 366         stw r4, SWCRR(r3)
 367
 368         /* reset */
 369         li      r4, 0x556C
 370         sth     r4, SWSRR@l(r3)
 371         li      r4, 0x0
 372         ori     r4, r4, 0xAA39
 373         sth     r4, SWSRR@l(r3)
 374 #else
 375         /* Disable the watchdog */
 376         /*----------------------*/
 377         lwz r4, SWCRR(r3)
 378         /*
 379          * Check to see if it's enabled for disabling: once disabled by s/w
 380          * it's not possible to re-enable it
 381          */
 382         andi. r4, r4, 0x4
 383         beq 1f
 384         xor r4, r4, r4
 385         stw r4, SWCRR(r3)
 386 1:
 387 #endif /* CONFIG_WATCHDOG */
 388
 389         /* Initialize the Hardware Implementation-dependent Registers */
 390         /* HID0 also contains cache control                     */
 391         /*------------------------------------------------------*/
 392         lis     r3, CONFIG_SYS_HID0_INIT@h
 393         ori     r3, r3, CONFIG_SYS_HID0_INIT@l
 394         SYNC
 395         mtspr   HID0, r3
 396
 397         lis     r3, CONFIG_SYS_HID0_FINAL@h
 398         ori     r3, r3, CONFIG_SYS_HID0_FINAL@l
 399         SYNC
 400         mtspr   HID0, r3
 401
 402         lis     r3, CONFIG_SYS_HID2@h
 403         ori     r3, r3, CONFIG_SYS_HID2@l
 404         SYNC
 405         mtspr   HID2, r3
 406         sync
 407         blr
 408
 409
 410 /* Cache functions.
 411  *
 412  * Note: requires that all cache bits in
 413  * HID0 are in the low half word.
 414  */
 415         .globl  icache_enable
 416 icache_enable:
 417         mfspr   r3, HID0
 418         ori     r3, r3, HID0_ICE
 419         lis     r4, 0
 420         ori     r4, r4, HID0_ILOCK
 421         andc    r3, r3, r4
 422         ori     r4, r3, HID0_ICFI
 423         isync
 424         mtspr   HID0, r4    /* sets enable and invalidate, clears lock */
 425         isync
 426         mtspr   HID0, r3        /* clears invalidate */
 427         blr
 428
 429         .globl  icache_disable
 430 icache_disable:
 431         mfspr   r3, HID0
 432         lis     r4, 0
 433         ori     r4, r4, HID0_ICE|HID0_ILOCK
 434         andc    r3, r3, r4
 435         ori     r4, r3, HID0_ICFI
 436         isync
 437         mtspr   HID0, r4     /* sets invalidate, clears enable and lock*/
 438         isync
 439         mtspr   HID0, r3        /* clears invalidate */
 440         blr
 441
 442         .globl  icache_status
 443 icache_status:
 444         mfspr   r3, HID0
 445         rlwinm  r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
 446         blr
 447
 448         .globl  dcache_enable
 449 dcache_enable:
 450         mfspr   r3, HID0
 451         li      r5, HID0_DCFI|HID0_DLOCK
 452         andc    r3, r3, r5
 453         mtspr   HID0, r3                /* no invalidate, unlock */
 454         ori     r3, r3, HID0_DCE
 455         ori     r5, r3, HID0_DCFI
 456         mtspr   HID0, r5                /* enable + invalidate */
 457         mtspr   HID0, r3                /* enable */
 458         sync
 459         blr
 460
 461         .globl  dcache_disable
 462 dcache_disable:
 463         mfspr   r3, HID0
 464         lis     r4, 0
 465         ori     r4, r4, HID0_DCE|HID0_DLOCK
 466         andc    r3, r3, r4
 467         ori     r4, r3, HID0_DCI
 468         sync
 469         mtspr   HID0, r4        /* sets invalidate, clears enable and lock */
 470         sync
 471         mtspr   HID0, r3        /* clears invalidate */
 472         blr
 473
 474         .globl  dcache_status
 475 dcache_status:
 476         mfspr   r3, HID0
 477         rlwinm  r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
 478         blr
 479
 480         .globl get_pvr
 481 get_pvr:
 482         mfspr   r3, PVR
 483         blr
 484
 485 /*-------------------------------------------------------------------*/
 486
 487 /*
 488  * void relocate_code (addr_sp, gd, addr_moni)
 489  *
 490  * This "function" does not return, instead it continues in RAM
 491  * after relocating the monitor code.
 492  *
 493  * r3 = dest
 494  * r4 = src
 495  * r5 = length in bytes
 496  * r6 = cachelinesize
 497  */
 498         .globl  relocate_code
 499 relocate_code:
 500         mr      r1,  r3         /* Set new stack pointer        */
 501         mr      r9,  r4         /* Save copy of Global Data pointer */
 502         mr      r10, r5         /* Save copy of Destination Address */
 503
 504         mr      r3,  r5                         /* Destination Address */
 505         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address */
 506         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 507         lwz     r5, GOT(__init_end)
 508         sub     r5, r5, r4
 509         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size */
 510
 511         /*
 512          * Fix GOT pointer:
 513          *
 514          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
 515          *              + Destination Address
 516          *
 517          * Offset:
 518          */
 519         sub     r15, r10, r4
 520
 521         /* First our own GOT */
 522         add     r14, r14, r15
 523         /* then the one used by the C code */
 524         add     r30, r30, r15
 525
 526         /*
 527          * Now relocate code
 528          */
 529         cmplw   cr1,r3,r4
 530         addi    r0,r5,3
 531         srwi.   r0,r0,2
 532         beq     cr1,4f          /* In place copy is not necessary */
 533         beq     7f              /* Protect against 0 count        */
 534         mtctr   r0
 535         bge     cr1,2f
 536         la      r8,-4(r4)
 537         la      r7,-4(r3)
 538
 539         /* copy */
 540 1:      lwzu    r0,4(r8)
 541         stwu    r0,4(r7)
 542         bdnz    1b
 543
 544         addi    r0,r5,3
 545         srwi.   r0,r0,2
 546         mtctr   r0
 547         la      r8,-4(r4)
 548         la      r7,-4(r3)
 549
 550         /* and compare */
 551 20:     lwzu    r20,4(r8)
 552         lwzu    r21,4(r7)
 553         xor. r22, r20, r21
 554         bne  30f
 555         bdnz    20b
 556         b 4f
 557
 558         /* compare failed */
 559 30:     li r3, 0
 560         blr
 561
 562 2:      slwi    r0,r0,2 /* re copy in reverse order ... y do we needed it? */
 563         add     r8,r4,r0
 564         add     r7,r3,r0
 565 3:      lwzu    r0,-4(r8)
 566         stwu    r0,-4(r7)
 567         bdnz    3b
 568
 569 /*
 570  * Now flush the cache: note that we must start from a cache aligned
 571  * address. Otherwise we might miss one cache line.
 572  */
 573 4:      cmpwi   r6,0
 574         add     r5,r3,r5
 575         beq     7f              /* Always flush prefetch queue in any case */
 576         subi    r0,r6,1
 577         andc    r3,r3,r0
 578         mr      r4,r3
 579 5:      dcbst   0,r4
 580         add     r4,r4,r6
 581         cmplw   r4,r5
 582         blt     5b
 583         sync                    /* Wait for all dcbst to complete on bus */
 584         mr      r4,r3
 585 6:      icbi    0,r4
 586         add     r4,r4,r6
 587         cmplw   r4,r5
 588         blt     6b
 589 7:      sync                    /* Wait for all icbi to complete on bus */
 590         isync
 591
 592 /*
 593  * We are done. Do not return, instead branch to second part of board
 594  * initialization, now running from RAM.
 595  */
 596         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 597         mtlr    r0
 598         blr
 599
 600 in_ram:
 601         /*
 602          * Relocation Function, r14 point to got2+0x8000
 603          *
 604          * Adjust got2 pointers, no need to check for 0, this code
 605          * already puts a few entries in the table.
 606          */
 607         li      r0,__got2_entries@sectoff@l
 608         la      r3,GOT(_GOT2_TABLE_)
 609         lwz     r11,GOT(_GOT2_TABLE_)
 610         mtctr   r0
 611         sub     r11,r3,r11
 612         addi    r3,r3,-4
 613 1:      lwzu    r0,4(r3)
 614         add     r0,r0,r11
 615         stw     r0,0(r3)
 616         bdnz    1b
 617
 618         /*
 619          * Now adjust the fixups and the pointers to the fixups
 620          * in case we need to move ourselves again.
 621          */
 622 2:      li      r0,__fixup_entries@sectoff@l
 623         lwz     r3,GOT(_FIXUP_TABLE_)
 624         cmpwi   r0,0
 625         mtctr   r0
 626         addi    r3,r3,-4
 627         beq     4f
 628 3:      lwzu    r4,4(r3)
 629         lwzux   r0,r4,r11
 630         add     r0,r0,r11
 631         stw     r10,0(r3)
 632         stw     r0,0(r4)
 633         bdnz    3b
 634 4:
 635 clear_bss:
 636         /*
 637          * Now clear BSS segment
 638          */
 639         lwz     r3,GOT(__bss_start)
 640         lwz     r4,GOT(_end)
 641
 642         cmplw   0, r3, r4
 643         beq     6f
 644
 645         li      r0, 0
 646 5:
 647         stw     r0, 0(r3)
 648         addi    r3, r3, 4
 649         cmplw   0, r3, r4
 650         bne     5b
 651 6:
 652         mr      r3, r9          /* Global Data pointer          */
 653         mr      r4, r10         /* Destination Address          */
 654         bl      board_init_r
 655
 656         /*
 657          * Copy exception vector code to low memory
 658          *
 659          * r3: dest_addr
 660          * r7: source address, r8: end address, r9: target address
 661          */
 662         .globl  trap_init
 663 trap_init:
 664         lwz     r7, GOT(_start)
 665         lwz     r8, GOT(_end_of_vectors)
 666
 667         li      r9, 0x100       /* reset vector at 0x100 */
 668
 669         cmplw   0, r7, r8
 670         bgelr                   /* return if r7>=r8 - just in case */
 671
 672         mflr    r4              /* save link register */
 673 1:
 674         lwz     r0, 0(r7)
 675         stw     r0, 0(r9)
 676         addi    r7, r7, 4
 677         addi    r9, r9, 4
 678         cmplw   0, r7, r8
 679         bne     1b
 680
 681         /*
 682          * relocate `hdlr' and `int_return' entries
 683          */
 684         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 685         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 686 2:
 687         bl      trap_reloc
 688         addi    r7, r7, 0x100           /* next exception vector */
 689         cmplw   0, r7, r8
 690         blt     2b
 691
 692         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 693         bl      trap_reloc
 694
 695         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 696         bl      trap_reloc
 697
 698         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 699         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 700 3:
 701         bl      trap_reloc
 702         addi    r7, r7, 0x100           /* next exception vector */
 703         cmplw   0, r7, r8
 704         blt     3b
 705
 706         li      r7, .L_Trace - _start + EXC_OFF_SYS_RESET
 707         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 708 4:
 709         bl      trap_reloc
 710         addi    r7, r7, 0x100           /* next exception vector */
 711         cmplw   0, r7, r8
 712         blt     4b
 713
 714         mfmsr   r3                      /* now that the vectors have */
 715         lis     r7, MSR_IP@h            /* relocated into low memory */
 716         ori     r7, r7, MSR_IP@l        /* MSR[IP] can be turned off */
 717         andc    r3, r3, r7              /* (if it was on) */
 718         SYNC                            /* Some chip revs need this... */
 719         mtmsr   r3
 720         SYNC
 721
 722         mtlr    r4                      /* restore link register    */
 723         blr
 724
 725         /*
 726          * Function: relocate entries for one exception vector
 727          */
 728 trap_reloc:
 729         lwz     r0, 0(r7)               /* hdlr ...             */
 730         add     r0, r0, r3              /*  ... += dest_addr    */
 731         stw     r0, 0(r7)
 732
 733         lwz     r0, 4(r7)               /* int_return ...       */
 734         add     r0, r0, r3              /*  ... += dest_addr    */
 735         stw     r0, 4(r7)
 736
 737         blr