cpu/mpc5xx/interrupts.c

   1 /*
   2  * (C) Copyright 2000-2002      Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   3  * (C) Copyright 2003           Martin Winistoerfer, martinwinistoerfer@gmx.ch.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation,
  21  */
  22
  23 /*
  24  * File:                interrupt.c
  25  *
  26  * Discription:         Contains interrupt routines needed by U-Boot
  27  *
  28  */
  29
  30 #include <common.h>
  31 #include <watchdog.h>
  32 #include <mpc5xx.h>
  33 #include <asm/processor.h>
  34
  35 /************************************************************************/
  36
  37 unsigned decrementer_count;     /* count value for 1e6/HZ microseconds  */
  38
  39 /************************************************************************/
  40
  41 struct interrupt_action {
  42         interrupt_handler_t *handler;
  43         void *arg;
  44 };
  45
  46 static struct interrupt_action irq_vecs[NR_IRQS];
  47
  48 /*
  49  * Local function prototypes
  50  */
  51 static __inline__ unsigned long get_msr (void)
  52 {
  53         unsigned long msr;
  54
  55         asm volatile ("mfmsr %0":"=r" (msr):);
  56
  57         return msr;
  58 }
  59
  60 static __inline__ void set_msr (unsigned long msr)
  61 {
  62         asm volatile ("mtmsr %0"::"r" (msr));
  63 }
  64
  65 static __inline__ unsigned long get_dec (void)
  66 {
  67         unsigned long val;
  68
  69         asm volatile ("mfdec %0":"=r" (val):);
  70
  71         return val;
  72 }
  73
  74
  75 static __inline__ void set_dec (unsigned long val)
  76 {
  77         asm volatile ("mtdec %0"::"r" (val));
  78 }
  79
  80 /*
  81  * Enable interrupts
  82  */
  83 void enable_interrupts (void)
  84 {
  85         set_msr (get_msr () | MSR_EE);
  86 }
  87
  88 /*
  89  * Returns flag if MSR_EE was set before
  90  */
  91 int disable_interrupts (void)
  92 {
  93         ulong msr = get_msr ();
  94
  95         set_msr (msr & ~MSR_EE);
  96         return ((msr & MSR_EE) != 0);
  97 }
  98
  99 /*
 100  * Initialise interrupts
 101  */
 102
 103 int interrupt_init (void)
 104 {
 105         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 106
 107         /* Decrementer used here for status led */
 108         decrementer_count = get_tbclk () / CFG_HZ;
 109
 110         /* Disable all interrupts */
 111         immr->im_siu_conf.sc_simask = 0;
 112
 113         set_dec (decrementer_count);
 114
 115         set_msr (get_msr () | MSR_EE);
 116         return (0);
 117 }
 118
 119 /*
 120  * Handle external interrupts
 121  */
 122 void external_interrupt (struct pt_regs *regs)
 123 {
 124         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 125         int irq;
 126         ulong simask, newmask;
 127         ulong vec, v_bit;
 128
 129         /*
 130          * read the SIVEC register and shift the bits down
 131          * to get the irq number
 132          */
 133         vec = immr->im_siu_conf.sc_sivec;
 134         irq = vec >> 26;
 135         v_bit = 0x80000000UL >> irq;
 136
 137         /*
 138          * Read Interrupt Mask Register and Mask Interrupts
 139          */
 140         simask = immr->im_siu_conf.sc_simask;
 141         newmask = simask & (~(0xFFFF0000 >> irq));
 142         immr->im_siu_conf.sc_simask = newmask;
 143
 144         if (!(irq & 0x1)) {             /* External Interrupt ?     */
 145                 ulong siel;
 146
 147                 /*
 148                  * Read Interrupt Edge/Level Register
 149                  */
 150                 siel = immr->im_siu_conf.sc_siel;
 151
 152                 if (siel & v_bit) {     /* edge triggered interrupt ?   */
 153                         /*
 154                          * Rewrite SIPEND Register to clear interrupt
 155                          */
 156                         immr->im_siu_conf.sc_sipend = v_bit;
 157                 }
 158         }
 159
 160         if (irq_vecs[irq].handler != NULL) {
 161                 irq_vecs[irq].handler (irq_vecs[irq].arg);
 162         } else {
 163                 printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
 164                                 irq, vec);
 165                 /* turn off the bogus interrupt to avoid it from now */
 166                 simask &= ~v_bit;
 167         }
 168         /*
 169          * Re-Enable old Interrupt Mask
 170          */
 171         immr->im_siu_conf.sc_simask = simask;
 172 }
 173
 174 /*
 175  * Install and free an interrupt handler
 176  */
 177 void irq_install_handler (int vec, interrupt_handler_t * handler,
 178                                                   void *arg)
 179 {
 180         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 181         /* SIU interrupt */
 182         if (irq_vecs[vec].handler != NULL) {
 183                 printf ("SIU interrupt %d 0x%x\n",
 184                         vec,
 185                         (uint) handler);
 186         }
 187         irq_vecs[vec].handler = handler;
 188         irq_vecs[vec].arg = arg;
 189         immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
 190 #if 0
 191         printf ("Install SIU interrupt for vector %d ==> %p\n",
 192                 vec, handler);
 193 #endif
 194 }
 195
 196 void irq_free_handler (int vec)
 197 {
 198         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 199         /* SIU interrupt */
 200 #if 0
 201         printf ("Free CPM interrupt for vector %d\n",
 202                 vec);
 203 #endif
 204         immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
 205         irq_vecs[vec].handler = NULL;
 206         irq_vecs[vec].arg = NULL;
 207 }
 208
 209 volatile ulong timestamp = 0;
 210
 211 /*
 212  *  Timer interrupt - gets called when  bit 0 of DEC changes from
 213  *  0. Decrementer is enabled with bit TBE in TBSCR.
 214  */
 215 void timer_interrupt (struct pt_regs *regs)
 216 {
 217         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 218
 219 #ifdef CONFIG_STATUS_LED
 220         extern void status_led_tick (ulong);
 221 #endif
 222 #if 0
 223         printf ("*** Timer Interrupt *** ");
 224 #endif
 225         /* Reset Timer Status Bit and Timers Interrupt Status */
 226         immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
 227         __asm__ ("nop");
 228         immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
 229
 230         /* Restore Decrementer Count */
 231         set_dec (decrementer_count);
 232
 233         timestamp++;
 234
 235 #ifdef CONFIG_STATUS_LED
 236         status_led_tick (timestamp);
 237 #endif /* CONFIG_STATUS_LED */
 238
 239 #if defined(CONFIG_WATCHDOG)
 240         /*
 241          * The shortest watchdog period of all boards
 242          * is approx. 1 sec, thus re-trigger watchdog at least
 243          * every 500 ms = CFG_HZ / 2
 244          */
 245         if ((timestamp % (CFG_HZ / 2)) == 0) {
 246                 reset_5xx_watchdog (immr);
 247         }
 248 #endif /* CONFIG_WATCHDOG */
 249 }
 250
 251 /*
 252  * Reset timer
 253  */
 254 void reset_timer (void)
 255 {
 256         timestamp = 0;
 257 }
 258
 259 /*
 260  * Get Timer
 261  */
 262 ulong get_timer (ulong base)
 263 {
 264         return (timestamp - base);
 265 }
 266
 267 /*
 268  * Set timer
 269  */
 270 void set_timer (ulong t)
 271 {
 272         timestamp = t;
 273 }