cpu/mpc5xxx/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc5xxx.h>
  26 #include <asm/io.h>
  27 #include <watchdog.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /*
  32  * Breath some life into the CPU...
  33  *
  34  * Set up the memory map,
  35  * initialize a bunch of registers.
  36  */
  37 void cpu_init_f (void)
  38 {
  39         volatile struct mpc5xxx_mmap_ctl *mm =
  40                 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
  41         volatile struct mpc5xxx_lpb *lpb =
  42                 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
  43         volatile struct mpc5xxx_gpio *gpio =
  44                 (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
  45         volatile struct mpc5xxx_xlb *xlb =
  46                 (struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
  47 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
  48         volatile struct mpc5xxx_cdm *cdm =
  49                 (struct mpc5xxx_cdm *) MPC5XXX_CDM;
  50 #endif  /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
  51 #if defined(CONFIG_WATCHDOG)
  52         volatile struct mpc5xxx_gpt *gpt0 =
  53                 (struct mpc5xxx_gpt *) MPC5XXX_GPT;
  54 #endif /* CONFIG_WATCHDOG */
  55         unsigned long addecr = (1 << 25); /* Boot_CS */
  56         /* Pointer is writable since we allocated a register for it */
  57         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  58
  59         /* Clear initial global data */
  60         memset ((void *) gd, 0, sizeof (gd_t));
  61
  62         /*
  63          * Memory Controller: configure chip selects and enable them
  64          */
  65 #if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
  66         out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
  67         out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
  68                                           CONFIG_SYS_BOOTCS_SIZE));
  69 #endif
  70 #if defined(CONFIG_SYS_BOOTCS_CFG)
  71         out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
  72 #endif
  73
  74 #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
  75         out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
  76         out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
  77                                          CONFIG_SYS_CS0_SIZE));
  78         /* CS0 and BOOT_CS cannot be enabled at once. */
  79         /*      addecr |= (1 << 16); */
  80 #endif
  81 #if defined(CONFIG_SYS_CS0_CFG)
  82         out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
  83 #endif
  84
  85 #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
  86         out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
  87         out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
  88                                          CONFIG_SYS_CS1_SIZE));
  89         addecr |= (1 << 17);
  90 #endif
  91 #if defined(CONFIG_SYS_CS1_CFG)
  92         out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
  93 #endif
  94
  95 #if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
  96         out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
  97         out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
  98                                          CONFIG_SYS_CS2_SIZE));
  99         addecr |= (1 << 18);
 100 #endif
 101 #if defined(CONFIG_SYS_CS2_CFG)
 102         out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
 103 #endif
 104
 105 #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
 106         out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
 107         out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
 108                                          CONFIG_SYS_CS3_SIZE));
 109         addecr |= (1 << 19);
 110 #endif
 111 #if defined(CONFIG_SYS_CS3_CFG)
 112         out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
 113 #endif
 114
 115 #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
 116         out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
 117         out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
 118                                           CONFIG_SYS_CS4_SIZE));
 119         addecr |= (1 << 20);
 120 #endif
 121 #if defined(CONFIG_SYS_CS4_CFG)
 122         out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
 123 #endif
 124
 125 #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
 126         out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
 127         out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
 128                                           CONFIG_SYS_CS5_SIZE));
 129         addecr |= (1 << 21);
 130 #endif
 131 #if defined(CONFIG_SYS_CS5_CFG)
 132         out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
 133 #endif
 134
 135         addecr |= 1;
 136 #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
 137         out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
 138         out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
 139                                           CONFIG_SYS_CS6_SIZE));
 140         addecr |= (1 << 26);
 141 #endif
 142 #if defined(CONFIG_SYS_CS6_CFG)
 143         out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
 144 #endif
 145
 146 #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
 147         out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
 148         out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
 149                                           CONFIG_SYS_CS7_SIZE));
 150         addecr |= (1 << 27);
 151 #endif
 152 #if defined(CONFIG_SYS_CS7_CFG)
 153         out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
 154 #endif
 155
 156 #if defined(CONFIG_SYS_CS_BURST)
 157         out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
 158 #endif
 159 #if defined(CONFIG_SYS_CS_DEADCYCLE)
 160         out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
 161 #endif
 162
 163         /* Enable chip selects */
 164         out_be32(&mm->ipbi_ws_ctrl, addecr);
 165         out_be32(&lpb->cs_ctrl, (1 << 24));
 166
 167         /* Setup pin multiplexing */
 168 #if defined(CONFIG_SYS_GPS_PORT_CONFIG)
 169         out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
 170 #endif
 171
 172         /* enable timebase */
 173         setbits_be32(&xlb->config, (1 << 13));
 174
 175         /* Enable snooping for RAM */
 176         setbits_be32(&xlb->config, (1 << 15));
 177         out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
 178
 179 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 180         /* Motorola reports IPB should better run at 133 MHz. */
 181         setbits_be32(&mm->ipbi_ws_ctrl, 1);
 182         /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
 183         addecr = in_be32(&cdm->cfg);
 184         addecr &= ~0x103;
 185 # if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
 186         /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
 187         addecr |= 0x01;
 188 # else
 189         /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
 190         addecr |= 0x02;
 191 # endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
 192         out_be32(&cdm->cfg, addecr);
 193 #endif  /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
 194         /* Configure the XLB Arbiter */
 195         out_be32(&xlb->master_pri_enable, 0xff);
 196         out_be32(&xlb->master_priority, 0x11111111);
 197
 198 #if defined(CONFIG_SYS_XLB_PIPELINING)
 199         /* Enable piplining */
 200         clrbits_be32(&xlb->config, (1 << 31));
 201 #endif
 202
 203 #if defined(CONFIG_WATCHDOG)
 204         /* Charge the watchdog timer - prescaler = 64k, count = 64k*/
 205         out_be32(&gpt0->cir, 0x0000ffff);
 206         out_be32(&gpt0->emsr, 0x9004);  /* wden|ce|timer_ms */
 207
 208         reset_5xxx_watchdog();
 209 #endif /* CONFIG_WATCHDOG */
 210 }
 211
 212 /*
 213  * initialize higher level parts of CPU like time base and timers
 214  */
 215 int cpu_init_r (void)
 216 {
 217         volatile struct mpc5xxx_intr *intr =
 218                 (struct mpc5xxx_intr *) MPC5XXX_ICTL;
 219
 220         /* mask all interrupts */
 221         out_be32(&intr->per_mask, 0xffffff00);
 222         setbits_be32(&intr->main_mask, 0x0001ffff);
 223         clrbits_be32(&intr->ctrl, 0x00000f00);
 224         /* route critical ints to normal ints */
 225         setbits_be32(&intr->ctrl, 0x00000001);
 226
 227 #if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
 228         /* load FEC microcode */
 229         loadtask(0, 2);
 230 #endif
 231
 232         return (0);
 233 }