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Patch by Mark Jonas, 01 Jul 2004:
[people/ms/u-boot.git] / cpu / mpc5xxx / fec.c
1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9 #include <common.h>
10 #include <mpc5xxx.h>
11 #include <malloc.h>
12 #include <net.h>
13 #include <miiphy.h>
14 #include "sdma.h"
15 #include "fec.h"
16
17 /* #define DEBUG 0x28 */
18
19 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC5xxx_FEC)
21
22 #if (DEBUG & 0x60)
23 static void tfifo_print(mpc5xxx_fec_priv *fec);
24 static void rfifo_print(mpc5xxx_fec_priv *fec);
25 #endif /* DEBUG */
26
27 #if (DEBUG & 0x40)
28 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
29 #endif
30
31 typedef struct {
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
36 } NBUF;
37
38 /********************************************************************/
39 #if (DEBUG & 0x2)
40 static void mpc5xxx_fec_phydump (void)
41 {
42 uint16 phyStatus, i;
43 uint8 phyAddr = CONFIG_PHY_ADDR;
44 uint8 reg_mask[] = {
45 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
46 /* regs to print: 0...7, 16...19, 21, 23, 24 */
47 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
48 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
49 #else
50 /* regs to print: 0...8, 16...20 */
51 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
52 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
53 #endif
54 };
55
56 for (i = 0; i < 32; i++) {
57 if (reg_mask[i]) {
58 miiphy_read(phyAddr, i, &phyStatus);
59 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
60 }
61 }
62 }
63 #endif
64
65 /********************************************************************/
66 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
67 {
68 int ix;
69 char *data;
70 static int once = 0;
71
72 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
73 if (!once) {
74 data = (char *)malloc(FEC_MAX_PKT_SIZE);
75 if (data == NULL) {
76 printf ("RBD INIT FAILED\n");
77 return -1;
78 }
79 fec->rbdBase[ix].dataPointer = (uint32)data;
80 }
81 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
82 fec->rbdBase[ix].dataLength = 0;
83 }
84 once ++;
85
86 /*
87 * have the last RBD to close the ring
88 */
89 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
90 fec->rbdIndex = 0;
91
92 return 0;
93 }
94
95 /********************************************************************/
96 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
97 {
98 int ix;
99
100 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
101 fec->tbdBase[ix].status = 0;
102 }
103
104 /*
105 * Have the last TBD to close the ring
106 */
107 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
108
109 /*
110 * Initialize some indices
111 */
112 fec->tbdIndex = 0;
113 fec->usedTbdIndex = 0;
114 fec->cleanTbdNum = FEC_TBD_NUM;
115 }
116
117 /********************************************************************/
118 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, FEC_RBD * pRbd)
119 {
120 /*
121 * Reset buffer descriptor as empty
122 */
123 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
124 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
125 else
126 pRbd->status = FEC_RBD_EMPTY;
127
128 pRbd->dataLength = 0;
129
130 /*
131 * Now, we have an empty RxBD, restart the SmartDMA receive task
132 */
133 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
134
135 /*
136 * Increment BD count
137 */
138 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
139 }
140
141 /********************************************************************/
142 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
143 {
144 FEC_TBD *pUsedTbd;
145
146 #if (DEBUG & 0x1)
147 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
148 fec->cleanTbdNum, fec->usedTbdIndex);
149 #endif
150
151 /*
152 * process all the consumed TBDs
153 */
154 while (fec->cleanTbdNum < FEC_TBD_NUM) {
155 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
156 if (pUsedTbd->status & FEC_TBD_READY) {
157 #if (DEBUG & 0x20)
158 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
159 #endif
160 return;
161 }
162
163 /*
164 * clean this buffer descriptor
165 */
166 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
167 pUsedTbd->status = FEC_TBD_WRAP;
168 else
169 pUsedTbd->status = 0;
170
171 /*
172 * update some indeces for a correct handling of the TBD ring
173 */
174 fec->cleanTbdNum++;
175 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
176 }
177 }
178
179 /********************************************************************/
180 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
181 {
182 uint8 currByte; /* byte for which to compute the CRC */
183 int byte; /* loop - counter */
184 int bit; /* loop - counter */
185 uint32 crc = 0xffffffff; /* initial value */
186
187 /*
188 * The algorithm used is the following:
189 * we loop on each of the six bytes of the provided address,
190 * and we compute the CRC by left-shifting the previous
191 * value by one position, so that each bit in the current
192 * byte of the address may contribute the calculation. If
193 * the latter and the MSB in the CRC are different, then
194 * the CRC value so computed is also ex-ored with the
195 * "polynomium generator". The current byte of the address
196 * is also shifted right by one bit at each iteration.
197 * This is because the CRC generatore in hardware is implemented
198 * as a shift-register with as many ex-ores as the radixes
199 * in the polynomium. This suggests that we represent the
200 * polynomiumm itself as a 32-bit constant.
201 */
202 for (byte = 0; byte < 6; byte++) {
203 currByte = mac[byte];
204 for (bit = 0; bit < 8; bit++) {
205 if ((currByte & 0x01) ^ (crc & 0x01)) {
206 crc >>= 1;
207 crc = crc ^ 0xedb88320;
208 } else {
209 crc >>= 1;
210 }
211 currByte >>= 1;
212 }
213 }
214
215 crc = crc >> 26;
216
217 /*
218 * Set individual hash table register
219 */
220 if (crc >= 32) {
221 fec->eth->iaddr1 = (1 << (crc - 32));
222 fec->eth->iaddr2 = 0;
223 } else {
224 fec->eth->iaddr1 = 0;
225 fec->eth->iaddr2 = (1 << crc);
226 }
227
228 /*
229 * Set physical address
230 */
231 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
232 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
233 }
234
235 /********************************************************************/
236 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
237 {
238 DECLARE_GLOBAL_DATA_PTR;
239 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
240 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
241
242 #if (DEBUG & 0x1)
243 printf ("mpc5xxx_fec_init... Begin\n");
244 #endif
245
246 /*
247 * Initialize RxBD/TxBD rings
248 */
249 mpc5xxx_fec_rbd_init(fec);
250 mpc5xxx_fec_tbd_init(fec);
251
252 /*
253 * Clear FEC-Lite interrupt event register(IEVENT)
254 */
255 fec->eth->ievent = 0xffffffff;
256
257 /*
258 * Set interrupt mask register
259 */
260 fec->eth->imask = 0x00000000;
261
262 /*
263 * Set FEC-Lite receive control register(R_CNTRL):
264 */
265 if (fec->xcv_type == SEVENWIRE) {
266 /*
267 * Frame length=1518; 7-wire mode
268 */
269 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
270 } else {
271 /*
272 * Frame length=1518; MII mode;
273 */
274 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
275 }
276
277 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
278 if (fec->xcv_type != SEVENWIRE) {
279 /*
280 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
281 * and do not drop the Preamble.
282 */
283 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
284 }
285
286 /*
287 * Set Opcode/Pause Duration Register
288 */
289 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
290
291 /*
292 * Set Rx FIFO alarm and granularity value
293 */
294 fec->eth->rfifo_cntrl = 0x0c000000;
295 fec->eth->rfifo_alarm = 0x0000030c;
296 #if (DEBUG & 0x22)
297 if (fec->eth->rfifo_status & 0x00700000 ) {
298 printf("mpc5xxx_fec_init() RFIFO error\n");
299 }
300 #endif
301
302 /*
303 * Set Tx FIFO granularity value
304 */
305 fec->eth->tfifo_cntrl = 0x0c000000;
306 #if (DEBUG & 0x2)
307 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
308 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
309 #endif
310
311 /*
312 * Set transmit fifo watermark register(X_WMRK), default = 64
313 */
314 fec->eth->tfifo_alarm = 0x00000080;
315 fec->eth->x_wmrk = 0x2;
316
317 /*
318 * Set individual address filter for unicast address
319 * and set physical address registers.
320 */
321 mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
322
323 /*
324 * Set multicast address filter
325 */
326 fec->eth->gaddr1 = 0x00000000;
327 fec->eth->gaddr2 = 0x00000000;
328
329 /*
330 * Turn ON cheater FSM: ????
331 */
332 fec->eth->xmit_fsm = 0x03000000;
333
334 #if defined(CONFIG_MPC5200)
335 /*
336 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
337 * work w/ the current receive task.
338 */
339 sdma->PtdCntrl |= 0x00000001;
340 #endif
341
342 /*
343 * Set priority of different initiators
344 */
345 sdma->IPR0 = 7; /* always */
346 sdma->IPR3 = 6; /* Eth RX */
347 sdma->IPR4 = 5; /* Eth Tx */
348
349 /*
350 * Clear SmartDMA task interrupt pending bits
351 */
352 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
353
354 /*
355 * Initialize SmartDMA parameters stored in SRAM
356 */
357 *(int *)FEC_TBD_BASE = (int)fec->tbdBase;
358 *(int *)FEC_RBD_BASE = (int)fec->rbdBase;
359 *(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
360 *(int *)FEC_RBD_NEXT = (int)fec->rbdBase;
361
362 /*
363 * Enable FEC-Lite controller
364 */
365 fec->eth->ecntrl |= 0x00000006;
366
367 #if (DEBUG & 0x2)
368 if (fec->xcv_type != SEVENWIRE)
369 mpc5xxx_fec_phydump ();
370 #endif
371
372 /*
373 * Enable SmartDMA receive task
374 */
375 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
376
377 #if (DEBUG & 0x1)
378 printf("mpc5xxx_fec_init... Done \n");
379 #endif
380
381 return 1;
382 }
383
384 /********************************************************************/
385 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
386 {
387 DECLARE_GLOBAL_DATA_PTR;
388 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
389 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
390
391 #if (DEBUG & 0x1)
392 printf ("mpc5xxx_fec_init_phy... Begin\n");
393 #endif
394
395 /*
396 * Initialize GPIO pins
397 */
398 if (fec->xcv_type == SEVENWIRE) {
399 /* 10MBit with 7-wire operation */
400 #if defined(CONFIG_TOTAL5200)
401 /* 7-wire and USB2 on Ethernet */
402 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
403 #else /* !CONFIG_TOTAL5200 */
404 /* 7-wire only */
405 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
406 #endif /* CONFIG_TOTAL5200 */
407 } else {
408 /* 100MBit with MD operation */
409 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
410 }
411
412 /*
413 * Clear FEC-Lite interrupt event register(IEVENT)
414 */
415 fec->eth->ievent = 0xffffffff;
416
417 /*
418 * Set interrupt mask register
419 */
420 fec->eth->imask = 0x00000000;
421
422 if (fec->xcv_type != SEVENWIRE) {
423 /*
424 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
425 * and do not drop the Preamble.
426 */
427 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
428 }
429
430 if (fec->xcv_type != SEVENWIRE) {
431 /*
432 * Initialize PHY(LXT971A):
433 *
434 * Generally, on power up, the LXT971A reads its configuration
435 * pins to check for forced operation, If not cofigured for
436 * forced operation, it uses auto-negotiation/parallel detection
437 * to automatically determine line operating conditions.
438 * If the PHY device on the other side of the link supports
439 * auto-negotiation, the LXT971A auto-negotiates with it
440 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
441 * support auto-negotiation, the LXT971A automatically detects
442 * the presence of either link pulses(10Mbps PHY) or Idle
443 * symbols(100Mbps) and sets its operating conditions accordingly.
444 *
445 * When auto-negotiation is controlled by software, the following
446 * steps are recommended.
447 *
448 * Note:
449 * The physical address is dependent on hardware configuration.
450 *
451 */
452 int timeout = 1;
453 uint16 phyStatus;
454
455 /*
456 * Reset PHY, then delay 300ns
457 */
458 miiphy_write(phyAddr, 0x0, 0x8000);
459 udelay(1000);
460
461 if (fec->xcv_type == MII10) {
462 /*
463 * Force 10Base-T, FDX operation
464 */
465 #if (DEBUG & 0x2)
466 printf("Forcing 10 Mbps ethernet link... ");
467 #endif
468 miiphy_read(phyAddr, 0x1, &phyStatus);
469 /*
470 miiphy_write(fec, phyAddr, 0x0, 0x0100);
471 */
472 miiphy_write(phyAddr, 0x0, 0x0180);
473
474 timeout = 20;
475 do { /* wait for link status to go down */
476 udelay(10000);
477 if ((timeout--) == 0) {
478 #if (DEBUG & 0x2)
479 printf("hmmm, should not have waited...");
480 #endif
481 break;
482 }
483 miiphy_read(phyAddr, 0x1, &phyStatus);
484 #if (DEBUG & 0x2)
485 printf("=");
486 #endif
487 } while ((phyStatus & 0x0004)); /* !link up */
488
489 timeout = 1000;
490 do { /* wait for link status to come back up */
491 udelay(10000);
492 if ((timeout--) == 0) {
493 printf("failed. Link is down.\n");
494 break;
495 }
496 miiphy_read(phyAddr, 0x1, &phyStatus);
497 #if (DEBUG & 0x2)
498 printf("+");
499 #endif
500 } while (!(phyStatus & 0x0004)); /* !link up */
501
502 #if (DEBUG & 0x2)
503 printf ("done.\n");
504 #endif
505 } else { /* MII100 */
506 /*
507 * Set the auto-negotiation advertisement register bits
508 */
509 miiphy_write(phyAddr, 0x4, 0x01e1);
510
511 /*
512 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
513 */
514 miiphy_write(phyAddr, 0x0, 0x1200);
515
516 /*
517 * Wait for AN completion
518 */
519 timeout = 5000;
520 do {
521 udelay(1000);
522
523 if ((timeout--) == 0) {
524 #if (DEBUG & 0x2)
525 printf("PHY auto neg 0 failed...\n");
526 #endif
527 return -1;
528 }
529
530 if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
531 #if (DEBUG & 0x2)
532 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
533 #endif
534 return -1;
535 }
536 } while (!(phyStatus & 0x0004));
537
538 #if (DEBUG & 0x2)
539 printf("PHY auto neg complete! \n");
540 #endif
541 }
542
543 }
544
545 #if (DEBUG & 0x2)
546 if (fec->xcv_type != SEVENWIRE)
547 mpc5xxx_fec_phydump ();
548 #endif
549
550
551 #if (DEBUG & 0x1)
552 printf("mpc5xxx_fec_init_phy... Done \n");
553 #endif
554
555 return 1;
556 }
557
558 /********************************************************************/
559 static void mpc5xxx_fec_halt(struct eth_device *dev)
560 {
561 #if defined(CONFIG_MPC5200)
562 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
563 #endif
564 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
565 int counter = 0xffff;
566
567 #if (DEBUG & 0x2)
568 if (fec->xcv_type != SEVENWIRE)
569 mpc5xxx_fec_phydump ();
570 #endif
571
572 /*
573 * mask FEC chip interrupts
574 */
575 fec->eth->imask = 0;
576
577 /*
578 * issue graceful stop command to the FEC transmitter if necessary
579 */
580 fec->eth->x_cntrl |= 0x00000001;
581
582 /*
583 * wait for graceful stop to register
584 */
585 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
586
587 /*
588 * Disable SmartDMA tasks
589 */
590 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
591 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
592
593 #if defined(CONFIG_MPC5200)
594 /*
595 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
596 * done. It doesn't work w/ the current receive task.
597 */
598 sdma->PtdCntrl &= ~0x00000001;
599 #endif
600
601 /*
602 * Disable the Ethernet Controller
603 */
604 fec->eth->ecntrl &= 0xfffffffd;
605
606 /*
607 * Clear FIFO status registers
608 */
609 fec->eth->rfifo_status &= 0x00700000;
610 fec->eth->tfifo_status &= 0x00700000;
611
612 fec->eth->reset_cntrl = 0x01000000;
613
614 /*
615 * Issue a reset command to the FEC chip
616 */
617 fec->eth->ecntrl |= 0x1;
618
619 /*
620 * wait at least 16 clock cycles
621 */
622 udelay(10);
623
624 #if (DEBUG & 0x3)
625 printf("Ethernet task stopped\n");
626 #endif
627 }
628
629 #if (DEBUG & 0x60)
630 /********************************************************************/
631
632 static void tfifo_print(mpc5xxx_fec_priv *fec)
633 {
634 uint16 phyAddr = CONFIG_PHY_ADDR;
635 uint16 phyStatus;
636
637 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
638 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
639
640 miiphy_read(phyAddr, 0x1, &phyStatus);
641 printf("\nphyStatus: 0x%04x\n", phyStatus);
642 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
643 printf("ievent: 0x%08x\n", fec->eth->ievent);
644 printf("x_status: 0x%08x\n", fec->eth->x_status);
645 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
646
647 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
648 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
649 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
650 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
651 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
652 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
653 }
654 }
655
656 static void rfifo_print(mpc5xxx_fec_priv *fec)
657 {
658 uint16 phyAddr = CONFIG_PHY_ADDR;
659 uint16 phyStatus;
660
661 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
662 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
663
664 miiphy_read(phyAddr, 0x1, &phyStatus);
665 printf("\nphyStatus: 0x%04x\n", phyStatus);
666 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
667 printf("ievent: 0x%08x\n", fec->eth->ievent);
668 printf("x_status: 0x%08x\n", fec->eth->x_status);
669 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
670
671 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
672 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
673 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
674 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
675 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
676 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
677 }
678 }
679 #endif /* DEBUG */
680
681 /********************************************************************/
682
683 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
684 int data_length)
685 {
686 /*
687 * This routine transmits one frame. This routine only accepts
688 * 6-byte Ethernet addresses.
689 */
690 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
691 FEC_TBD *pTbd;
692
693 #if (DEBUG & 0x20)
694 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
695 tfifo_print(fec);
696 #endif
697
698 /*
699 * Clear Tx BD ring at first
700 */
701 mpc5xxx_fec_tbd_scrub(fec);
702
703 /*
704 * Check for valid length of data.
705 */
706 if ((data_length > 1500) || (data_length <= 0)) {
707 return -1;
708 }
709
710 /*
711 * Check the number of vacant TxBDs.
712 */
713 if (fec->cleanTbdNum < 1) {
714 #if (DEBUG & 0x20)
715 printf("No available TxBDs ...\n");
716 #endif
717 return -1;
718 }
719
720 /*
721 * Get the first TxBD to send the mac header
722 */
723 pTbd = &fec->tbdBase[fec->tbdIndex];
724 pTbd->dataLength = data_length;
725 pTbd->dataPointer = (uint32)eth_data;
726 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
727 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
728
729 #if (DEBUG & 0x100)
730 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
731 #endif
732
733 /*
734 * Kick the MII i/f
735 */
736 if (fec->xcv_type != SEVENWIRE) {
737 uint16 phyStatus;
738 miiphy_read(0, 0x1, &phyStatus);
739 }
740
741 /*
742 * Enable SmartDMA transmit task
743 */
744
745 #if (DEBUG & 0x20)
746 tfifo_print(fec);
747 #endif
748 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
749 #if (DEBUG & 0x20)
750 tfifo_print(fec);
751 #endif
752 #if (DEBUG & 0x8)
753 printf( "+" );
754 #endif
755
756 fec->cleanTbdNum -= 1;
757
758 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
759 printf ("smartDMA ethernet Tx task enabled\n");
760 #endif
761 /*
762 * wait until frame is sent .
763 */
764 while (pTbd->status & FEC_TBD_READY) {
765 udelay(10);
766 #if (DEBUG & 0x8)
767 printf ("TDB status = %04x\n", pTbd->status);
768 #endif
769 }
770
771 return 0;
772 }
773
774
775 /********************************************************************/
776 static int mpc5xxx_fec_recv(struct eth_device *dev)
777 {
778 /*
779 * This command pulls one frame from the card
780 */
781 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
782 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
783 unsigned long ievent;
784 int frame_length, len = 0;
785 NBUF *frame;
786 char buff[FEC_MAX_PKT_SIZE];
787
788 #if (DEBUG & 0x1)
789 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
790 #endif
791 #if (DEBUG & 0x8)
792 printf( "-" );
793 #endif
794
795 /*
796 * Check if any critical events have happened
797 */
798 ievent = fec->eth->ievent;
799 fec->eth->ievent = ievent;
800 if (ievent & 0x20060000) {
801 /* BABT, Rx/Tx FIFO errors */
802 mpc5xxx_fec_halt(dev);
803 mpc5xxx_fec_init(dev, NULL);
804 return 0;
805 }
806 if (ievent & 0x80000000) {
807 /* Heartbeat error */
808 fec->eth->x_cntrl |= 0x00000001;
809 }
810 if (ievent & 0x10000000) {
811 /* Graceful stop complete */
812 if (fec->eth->x_cntrl & 0x00000001) {
813 mpc5xxx_fec_halt(dev);
814 fec->eth->x_cntrl &= ~0x00000001;
815 mpc5xxx_fec_init(dev, NULL);
816 }
817 }
818
819 if (!(pRbd->status & FEC_RBD_EMPTY)) {
820 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
821 ((pRbd->dataLength - 4) > 14)) {
822
823 /*
824 * Get buffer address and size
825 */
826 frame = (NBUF *)pRbd->dataPointer;
827 frame_length = pRbd->dataLength - 4;
828
829 #if (DEBUG & 0x20)
830 {
831 int i;
832 printf("recv data hdr:");
833 for (i = 0; i < 14; i++)
834 printf("%x ", *(frame->head + i));
835 printf("\n");
836 }
837 #endif
838 /*
839 * Fill the buffer and pass it to upper layers
840 */
841 memcpy(buff, frame->head, 14);
842 memcpy(buff + 14, frame->data, frame_length);
843 NetReceive(buff, frame_length);
844 len = frame_length;
845 }
846 /*
847 * Reset buffer descriptor as empty
848 */
849 mpc5xxx_fec_rbd_clean(fec, pRbd);
850 }
851 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
852 return len;
853 }
854
855
856 /********************************************************************/
857 int mpc5xxx_fec_initialize(bd_t * bis)
858 {
859 mpc5xxx_fec_priv *fec;
860 struct eth_device *dev;
861 char *tmp, *end;
862 char env_enetaddr[6];
863 int i;
864
865 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
866 dev = (struct eth_device *)malloc(sizeof(*dev));
867 memset(dev, 0, sizeof *dev);
868
869 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
870 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
871 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
872 #if defined(CONFIG_ICECUBE) || defined(CONFIG_PM520) || \
873 defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200)
874 # ifndef CONFIG_FEC_10MBIT
875 fec->xcv_type = MII100;
876 # else
877 fec->xcv_type = MII10;
878 # endif
879 #elif defined(CONFIG_TOTAL5200)
880 fec->xcv_type = SEVENWIRE;
881 #else
882 #error fec->xcv_type not initialized.
883 #endif
884
885 dev->priv = (void *)fec;
886 dev->iobase = MPC5XXX_FEC;
887 dev->init = mpc5xxx_fec_init;
888 dev->halt = mpc5xxx_fec_halt;
889 dev->send = mpc5xxx_fec_send;
890 dev->recv = mpc5xxx_fec_recv;
891
892 sprintf(dev->name, "FEC ETHERNET");
893 eth_register(dev);
894
895 /*
896 * Try to set the mac address now. The fec mac address is
897 * a garbage after reset. When not using fec for booting
898 * the Linux fec driver will try to work with this garbage.
899 */
900 tmp = getenv("ethaddr");
901 if (tmp) {
902 for (i=0; i<6; i++) {
903 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
904 if (tmp)
905 tmp = (*end) ? end+1 : end;
906 }
907 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
908 }
909
910 mpc5xxx_fec_init_phy(dev, bis);
911 return 1;
912 }
913
914 /* MII-interface related functions */
915 /********************************************************************/
916 int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
917 {
918 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
919 uint32 reg; /* convenient holder for the PHY register */
920 uint32 phy; /* convenient holder for the PHY */
921 int timeout = 0xffff;
922
923 /*
924 * reading from any PHY's register is done by properly
925 * programming the FEC's MII data register.
926 */
927 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
928 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
929
930 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
931
932 /*
933 * wait for the related interrupt
934 */
935 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
936
937 if (timeout == 0) {
938 #if (DEBUG & 0x2)
939 printf ("Read MDIO failed...\n");
940 #endif
941 return -1;
942 }
943
944 /*
945 * clear mii interrupt bit
946 */
947 eth->ievent = 0x00800000;
948
949 /*
950 * it's now safe to read the PHY's register
951 */
952 *retVal = (uint16) eth->mii_data;
953
954 return 0;
955 }
956
957 /********************************************************************/
958 int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
959 {
960 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
961 uint32 reg; /* convenient holder for the PHY register */
962 uint32 phy; /* convenient holder for the PHY */
963 int timeout = 0xffff;
964
965 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
966 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
967
968 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
969 FEC_MII_DATA_TA | phy | reg | data);
970
971 /*
972 * wait for the MII interrupt
973 */
974 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
975
976 if (timeout == 0) {
977 #if (DEBUG & 0x2)
978 printf ("Write MDIO failed...\n");
979 #endif
980 return -1;
981 }
982
983 /*
984 * clear MII interrupt bit
985 */
986 eth->ievent = 0x00800000;
987
988 return 0;
989 }
990
991 #if (DEBUG & 0x40)
992 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
993 {
994 int i;
995 char c;
996 unsigned int crc, count;
997
998 /*
999 * crc32 algorithm
1000 */
1001 /*
1002 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1003 */
1004 crc = crc_value;
1005
1006 for (i = len; --i >= 0;) {
1007 c = *string++;
1008 for (count = 0; count < 8; count++) {
1009 if ((c & 0x01) ^ (crc & 0x01)) {
1010 crc >>= 1;
1011 crc = crc ^ 0xedb88320;
1012 } else {
1013 crc >>= 1;
1014 }
1015 c >>= 1;
1016 }
1017 }
1018
1019 /*
1020 * In big endian system, do byte swaping for crc value
1021 */
1022 /**/ return crc;
1023 }
1024 #endif /* DEBUG */
1025
1026 #endif /* CONFIG_MPC5xxx_FEC */
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